A Real Time Programmable Encoder for Low Density Parity Check Code as specified in the IEEE P802.16E/D7 Standard and its Efficient Implementation on a DSP Processor

Zahid Khan, T. Arslan, Scott MacDougall
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引用次数: 11

Abstract

This paper presents a real time programmable irregular low density parity check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for frame sizes from 576 to 2304 and for five different code rates. H matrix is efficiently generated and stored for a particular frame size and code rate. The encoder is implemented on SC140 Processor and different optimization techniques are applied to enhance the throughput. With SC140, a reduction of 2.6 times in the number of effective MAC operations has been achieved, with further reduction in cycle counts possible. A pipelined architecture is also presented for possible ASIC or FPGA implementation.
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IEEE P802.16E/D7标准低密度奇偶校验码实时可编程编码器及其在DSP处理器上的高效实现
本文提出了一种符合IEEE P802.16E/D7标准的实时可编程不规则低密度奇偶校验(LDPC)编码器。编码器是可编程的帧大小从576到2304和五种不同的码率。H矩阵有效地生成和存储为特定的帧大小和码率。该编码器在SC140处理器上实现,并采用了不同的优化技术来提高吞吐量。使用SC140,有效MAC操作的数量减少了2.6倍,并可能进一步减少周期计数。流水线架构也提出了可能的ASIC或FPGA实现。
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