S. Harrison, D. Munteanu, U. Autran, A. Cros, R. Cerutti, T. Skotnicki
{"title":"Electrical characterization and modelling of high-performance SON DG MOSFETs","authors":"S. Harrison, D. Munteanu, U. Autran, A. Cros, R. Cerutti, T. Skotnicki","doi":"10.1109/ESSDER.2004.1356567","DOIUrl":null,"url":null,"abstract":"The electrical performances of highly scaled double-gate (DG) MOS transistors fabricated using a silicon-on-nothing (SON) process are presented. Very high drive current, high immunity to short-channel effects and perfect electrostatic integrity are obtained for ultra-thin and ultra-short devices, with silicon thicknesses down to 10 nm and channel lengths down to 30 nm. In addition, a dedicated compact modeling of the threshold voltage is proposed, taking into account short-channel effects, quantum mechanical confinement effects and temperature dependence. Finally, the impact of these confinement effects and ballistic transport on the operation of such ultimate devices is investigated using 2D quantum-mechanical simulations.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"CE-23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDER.2004.1356567","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
The electrical performances of highly scaled double-gate (DG) MOS transistors fabricated using a silicon-on-nothing (SON) process are presented. Very high drive current, high immunity to short-channel effects and perfect electrostatic integrity are obtained for ultra-thin and ultra-short devices, with silicon thicknesses down to 10 nm and channel lengths down to 30 nm. In addition, a dedicated compact modeling of the threshold voltage is proposed, taking into account short-channel effects, quantum mechanical confinement effects and temperature dependence. Finally, the impact of these confinement effects and ballistic transport on the operation of such ultimate devices is investigated using 2D quantum-mechanical simulations.
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