Vector compaction for power estimation with grouping and consecutive sampling techniques

Abstract

We propose a high efficiency and high accuracy power estimation method for CMOS combinational circuits with grouping and consecutive sampling techniques. We separate input pattern pairs into several groups according to their power characteristics. The consecutive sampling skill is applied to find a shorter subsequence from the original input sequence. Our experimental results demonstrate that the compaction ratios are 1,250(min) and 154(min) with power estimation errors of 3.31 %(avg) and 3.32%(avg) for two sampling strategies.