A highly scalable Π-shaped source/drain quasi-SOI MOS transistor

Abstract

This paper presents a highly scalable Π-shaped source/drain (Π-S/D) quasi-silicon-on-insulator (SOI) MOSFET and summarizes its preliminary characteristics compared with the recessed S/D SOI MOSFET and international technology roadmap for semiconductors (ITRS) roadmap values. SiGe-Si epitaxial growth, Si and SiGe etching, growth of epitaxial Si, and selective SiGe removal are used to form the Π-S/D in the quasi-SOI fabrication that no additional lithography mask is needed due mainly to the isolation-last-formed structures. Hence the advantages of the proposed quasi-SOI over conventional one, in device fabrication, are that the new quasi-SOI process can not only be completely compatible with the standard CMOS process, but can also achieve single-crystal silicon S/D regions. The three-dimensional numerical simulations carried out prove that a modified Π-S/D quasi-SOI transistor can meet ITRS requirements for high-performance devices in the 20 nm technology node and it means that the potential for planar bulk technology can still be used continuously.