Advanced CAD tools for ASIC testing

Abstract

The author describes a set of CAD tools for supporting the testing of application-specific integrated circuits (ASICs) designed with a scan-path technique. The tool set includes a project-specific design-rule checker, a scan designer generator, and a hardware-accelerated automatic test-pattern generation program. The tool set contains the following unique features: it supports a generalized scan-path design methodology; it makes it easy for a novice designer to do a scan design; and it generates test patterns which detect faults closely related to the failure in silicon.<>