M. Nafria, J. Diaz-Fortuny, P. Saraza-Canflanca, J. Martín-Martínez, E. Roca, R. Castro-López, R. Rodríguez, P. Martín-Lloret, A. Toro-Frías, D. Mateo, E. Barajas, X. Aragonès, F. Fernández
{"title":"Circuit reliability prediction: challenges and solutions for the device time-dependent variability characterization roadblock","authors":"M. Nafria, J. Diaz-Fortuny, P. Saraza-Canflanca, J. Martín-Martínez, E. Roca, R. Castro-López, R. Rodríguez, P. Martín-Lloret, A. Toro-Frías, D. Mateo, E. Barajas, X. Aragonès, F. Fernández","doi":"10.1109/LAEDC51812.2021.9437920","DOIUrl":null,"url":null,"abstract":"The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LAEDC51812.2021.9437920","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.