Product-Level Reliability Estimator with advanced CMOS technology

Abstract

A Product-Level Reliability Estimator (PLRE), which calculates failure rate of a chip as a function of use conditions, has been developed for the first time. Major wafer-level failure mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) and Electro Migration (EM) are included. By applying PLRE to the product with advanced CMOS technology, contributions from each block and each failure mechanism were quantitatively identified. It was shown that, at the target time-to-failure (TTF), gate dielectric (GD) TDDB takes the biggest portion of the failure rate, but the first failure comes with EM.