Extraction of token based VHDL models from old ASIC net lists

D. Soderberg
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Abstract

The author discusses the understanding of old ASIC components by extraction of VHDL models. To support the extraction process he has developed a pattern matching routine that can use both measured data or data from simulations. As he does not have access to tools that support automatic symbolic extraction, many processes had to be performed manually.
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从旧的ASIC网络列表中提取基于token的VHDL模型
作者通过VHDL模型的提取,讨论了对旧ASIC组件的理解。为了支持提取过程,他开发了一个模式匹配程序,可以使用测量数据或模拟数据。由于他无法访问支持自动符号提取的工具,因此许多过程必须手动执行。
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