A low-power area-efficient wide-range offset calibration technique for high-speed high-resolution comparator

Abstract

This paper presents a low-power, area-efficient and widerange offset calibration technique for the high-speed and highresolution comparator. The proposed technique with the low power charge pump significantly reduces the offset voltage (one sigma) from 39mV to 380μV. Without the requirements of capacitors array and extra reference voltage or bias currents, power dissipation and area are greatly reduced. Simulated results show that the comparator with calibration achieves 380μV offset operating at 3 GHz in 55nm CMOS technology with only 23.3μ W in calibration.