A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator

Abstract

In this paper, we present a pseudo-flash based digital low dropout (Digital LDO) voltage regulator. The novelty of our pseudo-flash based Digital LDO (PFD-LDO) voltage regulator lies in the fact that we use pseudo-flash (or alternately, flash) transistor subarrays for voltage regulation. By changing the threshold voltage (and thereby, the ON resistance) of these transistors, we can use the same design to meet different regulator specifications. The threshold voltage can be programmed either at the factory by the manufacturer or in the field by the user. This gives the manufacturer the ability to offer a family of LDO regulators with a single design, a significant economic advantage. In addition, aging effects and temperature variations are effectively erased since the threshold voltage of the pseudo-flash (or flash) transistors can be tuned to a fine degree in the field. Similarly, process variations can be cancelled after manufacturing in the factory. These advantages are absent in traditional LDO regulators. Our design uses two subarrays. A coarse subarray is used to reduce the recovery time and output voltage overshoot/undershoot, while a fine subarray regulates the output voltage, minimizing the output voltage ripple. Unlike state-of-the-art LDO regulators, our design can realize multiple specifications with the same circuit. For example, we demonstrate that the Vout of the proposed PFD-LDO regulator can range from 0.7V to 1.7V when the supply voltage VIN ranges from 0.8V to 1.8V, using the same circuit design. Over this voltage range, the proposed PFD-LDO regulator achieves Vshoot < 144mV, trec < 0.41µs and Vripple < 7.3mV when the Imax ranges from 15mA to 250mA.