Predictive models and CAD methodology for pattern dependent variability

Abstract

Lithography, etch and stress are dominant effects impacting the functionality and performance of designs at 65 nm and below. This paper discusses pattern dependent variability caused by these effects and discusses a model-based approach to extracting this variability. A methodology to gauge the extent of this pattern dependent variability for standard cells is presented by looking at the difference in transistor parameters when the cell is analyze in different contexts. A full-chip methodology that addresses the delay change due to systematic varation has been introduced to analyze and repair a 65 nm digital design.