Static analysis of transaction-level models

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI:10.1145/775832.775950

G. Agosta, F. Bruschi, D. Sciuto

引用次数: 12

Abstract

The introduction of design languages, such as SystemC 2.0, that allow the modeling of digital systems at the transaction level will impose some major changes to the design flows. Since these formalisms allow for a higher level of abstraction in the systems description, new methodological tools will be needed to support all design phases. The goal of this paper is twofold: first we formalize in an abstract way a significant set of features of a Transaction Level Model, according to the SystemC 2.0 formalism. Then, upon this model we define numerical metrics that can provide useful information in the analysis of the system-level specifications. In particular these metrics are useful in the design exploration phase, to define the main characteristics of the hardware and software architectures.

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事务级模型的静态分析

设计语言的引入，例如SystemC 2.0，允许在事务级别对数字系统进行建模，这将对设计流程造成一些重大变化。由于这些形式化允许在系统描述中进行更高层次的抽象，因此需要新的方法工具来支持所有的设计阶段。本文的目标有两个:首先，我们根据SystemC 2.0的形式化，以抽象的方式形式化了事务级模型的一组重要特征。然后，在这个模型的基础上，我们定义了可以在系统级规范的分析中提供有用信息的数值度量。特别是，这些度量在设计探索阶段非常有用，可以定义硬件和软件架构的主要特征。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

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