A high speed VLSI chip for data compression

Abstract

The authors describe a high-speed VLSI chip that implements the LZ technique for data compression. The LZ technique for data compression involves two basic steps, parsing and coding. The LZ-based compression method is a powerful technique and gives high compression efficiency for text and image data. The architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throughput. Hardware schemes are proposed for decompressing data that has been compressed using the LZ method. The data compression hardware can be integrated into real-time systems so that data can be compressed and decompressed on-the-fly. A prototype CMOS VLSI chip has been designed and fabricated using CMOS 2-micron technology implementing a systolic array of nine processors. The proposed hardware can yield compression rates of about 20 million characters per second.<>