R. Damodaran, T. Anderson, S. Agarwala, R. Venkatasubramanian, M. Gill, Dhileep Gopalakrishnan, A. Hill, A. Chachad, D. Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, S. Moharil, Matthew D. Pierson, Steven Mullinnix, Hung Ong, D. Thompson, Krishna Gurram, O. Olorode, Nuruddin Mahmood, Jose Flores, A. Rajagopal, Soujanya Narnur, Daniel Wu, Alan Hales, Kyle Peavy, Robert Sussman
{"title":"A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS","authors":"R. Damodaran, T. Anderson, S. Agarwala, R. Venkatasubramanian, M. Gill, Dhileep Gopalakrishnan, A. Hill, A. Chachad, D. Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, S. Moharil, Matthew D. Pierson, Steven Mullinnix, Hung Ong, D. Thompson, Krishna Gurram, O. Olorode, Nuruddin Mahmood, Jose Flores, A. Rajagopal, Soujanya Narnur, Daniel Wu, Alan Hales, Kyle Peavy, Robert Sussman","doi":"10.1109/VLSID.2012.85","DOIUrl":null,"url":null,"abstract":"The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 25th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2012.85","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.
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