Design and Performance of High-speed Low-Offset CMOS Double-Tail Dynamic Comparators using Offset Control scheme

Abstract

This paper addresses novel design of complementary metal oxide semiconductor (CMOS) Double tail dynamic comparators (DoTDCs) using offset control scheme. The offset control scheme adopted the phenomena of time-domain bulk-tuning to input transistors. The modification in offset control scheme and comparator core is done to reduce leakage through the bulk node and other issue noticed in design. The novel phase detector and charge pump are also proposed for high-speed, low power. Based on the proposed phase detector and charge pump, offset control scheme is designed, and using this two different DoTDCs, named as DoTDC-I and DoTDC-II are proposed. To verify the outcomes, they are simulated in SPECTRE at 0.8V of the supply voltage at 45nm CMOS technology node. Monte-Carlo simulation is done to obtain the offset voltage. The result shows that the offset-voltage is reduced from 1.608mV to 0.911mV in DoTDCI and from 1.694mV to 1.426mV in DoTDC-II structures using said control scheme.