VLSI architecture of digital matched filter and prime interleaver for W-CDMA

Abstract

A VLSI architecture dedicated to W-CDMA (Wideband Code Division Multiple Access) baseband modem is described, with the main theme focused on the cell searcher and PIL (Prime InterLeaver). A search algorithm is refined for the cell searcher to minimize the circuit size, maintaining the operating throughput. In addition, a time-shared scheme is adopted for the turbo encoding/decoding, aiming at the maximization of the hardware sharing in the encoding/decoding process. Finally, implementation results are shown to demonstrate that the proposed architecture can contribute much toward the practical low-power implementation of W-CDMA baseband modem LSI.