Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-κ gate dielectric stacks

Abstract

Grain boundary (GB) microstructural defects in polycrystalline high-? dielectric thin films may cause localized non-random trap generation during the percolation breakdown (BD) process. We study the effect of this non-random trap generation on the reliability statistics of the metal gate (MG) - high-κ (HK) stack. For the first time, we propose a fundamental physics-based Kinetic Monte Carlo (KMC) model considering the thermodynamics and kinetics of bond breaking, generation of oxygen vacancy traps and simulating the trap evolution process in a dual-layer HK - interfacial layer (IL) gate stack. Our simulation model helps explain the non-Weibull distribution trends for time dependent dielectric breakdown data (TDDB) and also determine the sequence of BD which is found to be independent of the thickness ratio of (tHK : tIL) and gate voltage (Vg). Results show that the IL layer is always more susceptible to early percolation and circuit level failure may only be caused by multiple soft BD (SBD) events in the IL layer. The possibility of a sequential IL → HK breakdown is very unlikely for operating voltage conditions of Vop = 1V.