{"title":"A hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications","authors":"Angelo Kuti Lusala, J. Legat","doi":"10.1109/NORCHIP.2010.5669434","DOIUrl":null,"url":null,"abstract":"In this paper we propose a hybrid network-on-chip which combines Spatial Division Multiplexing “SDM”-based circuit switching and packet switching in order to efficiently and separately handle streaming and best-effort traffics generated by real-time applications. The SDM technique is used in circuit-switched sub-network in order to increase path diversity, thereby improving throughput and mitigating low resource utilization, while packet-switched sub-network is kept as simple as possible. In this way QoS is simply guaranteed without having to share resources, which often leads to a complex design. The proposed hybrid router architecture has been synthesized in FPGA and ASIC, and results show that a practical hybrid network-on-chip can then be built using the proposed approach.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"NORCHIP 2010","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHIP.2010.5669434","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this paper we propose a hybrid network-on-chip which combines Spatial Division Multiplexing “SDM”-based circuit switching and packet switching in order to efficiently and separately handle streaming and best-effort traffics generated by real-time applications. The SDM technique is used in circuit-switched sub-network in order to increase path diversity, thereby improving throughput and mitigating low resource utilization, while packet-switched sub-network is kept as simple as possible. In this way QoS is simply guaranteed without having to share resources, which often leads to a complex design. The proposed hybrid router architecture has been synthesized in FPGA and ASIC, and results show that a practical hybrid network-on-chip can then be built using the proposed approach.