A 72.6 dB SNDR 14b 100 MSPS Ring Amplifier Based Pipelined SAR ADC with Dynamic Deadzone Control in 16 nm CMOS

Abstract

Ring amplifiers have emerged as scaling friendly amplification alternatives to conventional OTA-based switched capacitor residue amplifiers. To address potential instability in feedback as the supply voltage is shrunk in deep nanoscale CMOS, we merge a dynamic deadzone control circuit into the second stage inverter structure of a three stage amplifier, enhancing stability and enabling operation at ultra-low supply voltage of 0.75 V, thereby significantly reducing power consumption. A technique to enable the amplifier to perform both coarse estimation and fine settling is also disclosed. A 14 bit 100 MSPS pipelined SAR ADC prototype in 16nm consumes 2.5 mW and achieves measured SNDR and SFDR of 72.6 dB and 86.5 dB respectively, close to Nyquist input frequency, yielding a SNDR based FOM of 175.6 dB without calibration.