Systems-on-chip: Use of test data compression technique for reducing test time

Abstract

During the production phase of microelectronics systems, one of the fundamental steps is to check if the system works fine. This step is called the test of integrated circuits. Furthermore, cost reduction of these tests has become a major axe of research in microelectronics. Several techniques allow reducing these costs, whether by reducing the test data volume (vertical compression) whether by reducing the need in Automatic Test Equipment to send the test data to the Circuit Under Test (horizontal compression). This is called Test Data Compression. But most of these techniques can only be applied to single cores. Yet actual systems-on-chip are now composed of numerous cores. This paper first presents a new horizontal compression method that is perfectly applicable in the multiple-cores systems framework. Then, two applications of this method to systems (1/bus-based and 2/Network-on-Chip-based systems) are presented. Compression allows here an increase in test parallelism and thus a decrease in test time of the whole system.