A Novel RISC Architecture for High-Speed Floating-Point Signal Processing

Abstract

This paper describes the Floating-point digital Signal Processor of UCL, the FSPU, which is a single chip 22-bit signal and speech processor. The FSPU has been conceived according to a RISC philosophy and is based on a novel Processing Unit that achieves very high computation throughputs, while taking the greatest advantage of the wide dynamic range and precision features of the floating-point arithmetic. The developed architecture is intended to go beyond the limits of the standard general-purpose DSP implementations and to make the floating-point arithmetic more attractive on speed level. A 3 ¿m CMOS prototype has been realized.