High-speed system bus for a SoC network processing platform

Abstract

Interconnecting modules in a SoC platform requires modules compatibility. Several solutions are available, but they either lack the necessary throughput or the flexibility. This paper proposes an interconnection architecture for a flexible on-chip high-performance communication medium that can provide variable bandwidth. It is based on the AHB AMBA bus. The proposed architecture has been implemented in the Seamless environment and laid out using a 0.18 /spl mu/m CMOS with Cadence tools to validate the proposed concept.