In this paper, we propose an optimal VLSI implementation for a class of programmable FIR filters with binary coefficients, whose architecture is based on a parameterized divide and conquer approach. The proposed design is shown to be easily extendable to FIR filters with multibit coefficients with arbitrary sign. The area efficiency achieved in comparison to direct form realization is demonstrated by VLSI implementation examples, synthesized in TSMC 0.18 micrometer single poly six metal layer CMOS process using state-of-art VLSI EDA tools. A control algorithm to configure the proposed implementation scheme is discussed.
{"title":"An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach","authors":"T. Poonnen, A. Fam","doi":"10.1109/ICM.2003.238420","DOIUrl":"https://doi.org/10.1109/ICM.2003.238420","url":null,"abstract":"In this paper, we propose an optimal VLSI implementation for a class of programmable FIR filters with binary coefficients, whose architecture is based on a parameterized divide and conquer approach. The proposed design is shown to be easily extendable to FIR filters with multibit coefficients with arbitrary sign. The area efficiency achieved in comparison to direct form realization is demonstrated by VLSI implementation examples, synthesized in TSMC 0.18 micrometer single poly six metal layer CMOS process using state-of-art VLSI EDA tools. A control algorithm to configure the proposed implementation scheme is discussed.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130910964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, parasitic effect of CMOS differential LNA is discussed. The sources of parasitic effects are MOS transistor, differential structure, pad, and spiral inductor. Those parasitic effects are analyzed, and differential LNA is simulated with parasitic effects and measured.
{"title":"Parasitic effect analysis for a differential LNA design","authors":"Moon-sun Kim, J. Yi, Hyung-Joun Yoo","doi":"10.1109/ICM.2003.238558","DOIUrl":"https://doi.org/10.1109/ICM.2003.238558","url":null,"abstract":"In this paper, parasitic effect of CMOS differential LNA is discussed. The sources of parasitic effects are MOS transistor, differential structure, pad, and spiral inductor. Those parasitic effects are analyzed, and differential LNA is simulated with parasitic effects and measured.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124478751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Flip-flops are essential elements of a design from both delay and energy aspects. A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes are promising approaches for future designs. Recently, there has been published several energy recovery flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. However, there has not been shown any extensive power and delay comparison between energy-recovery and square clock flip-flops. We compare the energy recovery flip-flops with square wave clock flip-flops in terms of power, delay, and area. Based on the simulation results using BPTM 0.18 /spl mu/m CMOS technology, at a frequency of 200 MHz, the differential energy recovery flip-flops exhibit more than 14% delay reduction and power reduction of more than 43% compared to the differential square-wave clock flip-flops. The single-ended energy recovery flip-flops show more than 22% delay reduction and power reduction of more than 16% compared to the single-ended square wave clock flip-flops.
{"title":"Comparative energy and delay of energy recovery and square wave clock flip-flops for high-performance and low-power applications","authors":"A. Ghadiri, H. Mahmoodi-Meimand","doi":"10.1109/ICM.2003.238362","DOIUrl":"https://doi.org/10.1109/ICM.2003.238362","url":null,"abstract":"Flip-flops are essential elements of a design from both delay and energy aspects. A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes are promising approaches for future designs. Recently, there has been published several energy recovery flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. However, there has not been shown any extensive power and delay comparison between energy-recovery and square clock flip-flops. We compare the energy recovery flip-flops with square wave clock flip-flops in terms of power, delay, and area. Based on the simulation results using BPTM 0.18 /spl mu/m CMOS technology, at a frequency of 200 MHz, the differential energy recovery flip-flops exhibit more than 14% delay reduction and power reduction of more than 43% compared to the differential square-wave clock flip-flops. The single-ended energy recovery flip-flops show more than 22% delay reduction and power reduction of more than 16% compared to the single-ended square wave clock flip-flops.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126060455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Evolutionary computation is a new field of research in which hardware design is pursued by deriving inspiration from biological organisms. This new paradigm is expected to radically change the synthesis procedures in a way that allows discovering novel designs and/or more efficient circuits. In this paper, a multi objective optimization strategy for design of arithmetic circuits based on Ant Colony optimization algorithm is presented. Results are compared with those obtained using other techniques.
{"title":"Ant colony algorithm for evolutionary design of arithmetic circuits","authors":"M. Abd-El-Barr, S. M. Sait, Bambang A. B. Sarif","doi":"10.1109/ICM.2003.238612","DOIUrl":"https://doi.org/10.1109/ICM.2003.238612","url":null,"abstract":"Evolutionary computation is a new field of research in which hardware design is pursued by deriving inspiration from biological organisms. This new paradigm is expected to radically change the synthesis procedures in a way that allows discovering novel designs and/or more efficient circuits. In this paper, a multi objective optimization strategy for design of arithmetic circuits based on Ant Colony optimization algorithm is presented. Results are compared with those obtained using other techniques.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114894974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper deals with the computation of some elementary functions using piecewise Minimax approximation and small tables. The strength of the method is that the same scheme is used to compute all the elementary functions with similar delay and accuracy of lulp (unit in last place). The hardware implementation of this method requires one multiplier and one adder chosen among those available in the Virtex-II FPGA as they present the highest performances concerning the delay and the area. The method has been implemented in a recursive structure which operates at a frequency of over than 25 Mhz.
{"title":"Multifunction generator using Horner scheme and small tables","authors":"H. Bessalah, N. Anane, M. Anane","doi":"10.1109/ICM.2003.238618","DOIUrl":"https://doi.org/10.1109/ICM.2003.238618","url":null,"abstract":"This paper deals with the computation of some elementary functions using piecewise Minimax approximation and small tables. The strength of the method is that the same scheme is used to compute all the elementary functions with similar delay and accuracy of lulp (unit in last place). The hardware implementation of this method requires one multiplier and one adder chosen among those available in the Virtex-II FPGA as they present the highest performances concerning the delay and the area. The method has been implemented in a recursive structure which operates at a frequency of over than 25 Mhz.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128780529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present the construction of a self-timed, multiple-input, priority arbiter with lower latency than existing solutions. The arbiter also overcomes the problem of allowing a contender to obtain over 50% of the resources allocation in a self-timed system by using downstream knowledge to trigger the arbitration. The arbiter is especially suited to the provision of quality of service in a self-timed interconnect.
{"title":"An asynchronous low latency arbiter for Quality of Service (QoS) applications","authors":"T. Felicijan, J. Bainbridge, S. Furber","doi":"10.1109/ICM.2003.238427","DOIUrl":"https://doi.org/10.1109/ICM.2003.238427","url":null,"abstract":"In this paper we present the construction of a self-timed, multiple-input, priority arbiter with lower latency than existing solutions. The arbiter also overcomes the problem of allowing a contender to obtain over 50% of the resources allocation in a self-timed system by using downstream knowledge to trigger the arbitration. The arbiter is especially suited to the provision of quality of service in a self-timed interconnect.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127477594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, a group of novel devices based on conducting interfaces is proposed. These conducting interfaces can be implemented by using the inversion layer of MOS structures, trapped charges or depletion layer charges. It has been shown that these structures can support surface electromagnetic waves. In this paper, the coupling of surface electromagnetic waves supported by conducting interfaces is analyzed and an analytical formula is driven by using the coupled mode theory. It is shown that one can program the coupling length of this structure by applying a transverse voltage and obtain a new type of optical modulator. The results obtained by coupled mode theory are verified by solving Maxwell's equations and applying appropriate boundary conditions.
{"title":"Programmable surface electromagnetic wave coupler","authors":"K. Mehrany, B. Rashidian","doi":"10.1109/ICM.2003.238500","DOIUrl":"https://doi.org/10.1109/ICM.2003.238500","url":null,"abstract":"Recently, a group of novel devices based on conducting interfaces is proposed. These conducting interfaces can be implemented by using the inversion layer of MOS structures, trapped charges or depletion layer charges. It has been shown that these structures can support surface electromagnetic waves. In this paper, the coupling of surface electromagnetic waves supported by conducting interfaces is analyzed and an analytical formula is driven by using the coupled mode theory. It is shown that one can program the coupling length of this structure by applying a transverse voltage and obtain a new type of optical modulator. The results obtained by coupled mode theory are verified by solving Maxwell's equations and applying appropriate boundary conditions.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125194102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present the design and implementation procedures of a CMOS integrated intermediate frequency (IF) limiting amplifier, which is characterized by its high sensitivity (10 /spl mu/V), high gain (110 dB at 10.7 MHz), low cost, and low output offset voltage (/spl sim/2 /spl mu/V). The amplifier is designed for high sensitivity hearing aids, but can be also utilized in various mobile FM/FSK transceivers. The IF/limiting amplifier consist of 8 direct-coupled differential stages and a limiter stage. A negative feedback network with smart mixing circuit is provided for gain control and automatic offset cancellation. Direct coupling of intermediate stages eliminated the need to integrate so many coupling capacitors, which consume large die area. The amplifier is integrated using 0.8 /spl mu/m standard CMOS technology and occupies a die area of 0.2 mm/sup 2/. The IF/limiter amplifier limits its output to 10 mV at 50 /spl Omega/ load, while consuming no more than 22 mW from a 3.3 V supply.
{"title":"A low-cost 110 dB CMOS IF/limiter amplifier with offset cancellation","authors":"D.Y. Gouda, M. Atef, A. El-Sabban, M. El-Saba","doi":"10.1109/ICM.2003.238560","DOIUrl":"https://doi.org/10.1109/ICM.2003.238560","url":null,"abstract":"In this paper we present the design and implementation procedures of a CMOS integrated intermediate frequency (IF) limiting amplifier, which is characterized by its high sensitivity (10 /spl mu/V), high gain (110 dB at 10.7 MHz), low cost, and low output offset voltage (/spl sim/2 /spl mu/V). The amplifier is designed for high sensitivity hearing aids, but can be also utilized in various mobile FM/FSK transceivers. The IF/limiting amplifier consist of 8 direct-coupled differential stages and a limiter stage. A negative feedback network with smart mixing circuit is provided for gain control and automatic offset cancellation. Direct coupling of intermediate stages eliminated the need to integrate so many coupling capacitors, which consume large die area. The amplifier is integrated using 0.8 /spl mu/m standard CMOS technology and occupies a die area of 0.2 mm/sup 2/. The IF/limiter amplifier limits its output to 10 mV at 50 /spl Omega/ load, while consuming no more than 22 mW from a 3.3 V supply.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126150855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a technique for the optimal design of signal processing system. This technique optimizes area of the design subject to throughput constraints. An Integer Linear Programming (IP) model is formed and mathematical modeling approach is used for solving the constrained optimization problem. The approach adds more sample points in the discrete design space by allowing hybrid architectures. The solution from the IP solver is passed to a code generator engine, which generates RTL Verilog code of the final design.
{"title":"Optimal digital design of signal processing applications using hybrid architectures","authors":"H. Jamal, S. Khan, K. Mahmood","doi":"10.1109/ICM.2003.238251","DOIUrl":"https://doi.org/10.1109/ICM.2003.238251","url":null,"abstract":"This paper presents a technique for the optimal design of signal processing system. This technique optimizes area of the design subject to throughput constraints. An Integer Linear Programming (IP) model is formed and mathematical modeling approach is used for solving the constrained optimization problem. The approach adds more sample points in the discrete design space by allowing hybrid architectures. The solution from the IP solver is passed to a code generator engine, which generates RTL Verilog code of the final design.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122427978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A low-voltage low-power analog low-distortion low-noise preamplifier is presented. It has been designed for a single supply voltage of /spl plusmn/1.2V, whereas its average power consumption for the complete preamplifier is 4 /spl mu/ watts. The design is suitable for most applications in portable telephone equipment, portable receivers, hearing aid, etc. The circuit simulation results of the most important properties are presented.
{"title":"Design of low-voltage low-power preamplifier for hearing aid devices","authors":"S.A. Saleh, H. Elsemary, H. Hamed, M. Azzam","doi":"10.1109/ICM.2003.238248","DOIUrl":"https://doi.org/10.1109/ICM.2003.238248","url":null,"abstract":"A low-voltage low-power analog low-distortion low-noise preamplifier is presented. It has been designed for a single supply voltage of /spl plusmn/1.2V, whereas its average power consumption for the complete preamplifier is 4 /spl mu/ watts. The design is suitable for most applications in portable telephone equipment, portable receivers, hearing aid, etc. The circuit simulation results of the most important properties are presented.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114191909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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