Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET

Abstract

A novel latch-based comparator is proposed for Successive Approximation (SA) Analog to Digital Convertor(ADC) with sub-32nm Double Gate MOSFETs(DG-MOSFET). The regeneration time of the latch is improved by using an extra positive feedback which uses the threshold voltage modulation property of DG-MOSFET. Simulation of the proposed comparator with CEA-LETI's DG-MOSFETmodels resulted in a delay of 25ps. The average power dissipation over one clock period is ≤ 1μW up to the clock frequency of 100MHz, which increases as frequency is increased resulting in an average power of 6.54μW at 1GHz, for an input voltage differential of 50mV.