Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs

Abstract

We present an experimental analysis of the sensitivity of SRAM-based FPGAs to alpha particles. We study how the different resources inside the FPGA (LUTs, MUXs, PIPs, etc. ) are affected by alpha-induced SEUs, assessing the cross section for the configuration memory cells controlling each of them. We then show two case studies, a chain of FIR filters and a series of soft microcontrollers implemented in the FPGA, measuring the rate of functional interruptions during exposure to a constant flux of alpha particles. The designs are then hardened using triplication with a single final voter, with intermediate voters, and finally including also feedback voters. The robustness of each hardening solution is discussed, analyzing the trade-off between area and fault-tolerance as a function of the number of SEUs in the configuration memory. An analytical model to predict the cross section of a given design with and without hardening solutions is finally proposed, starting from the experimental data.