Testing methods for integrated circuit of phase locked loops

Abstract

The conventional integrated circuit phase locked loop (PLL) has few output signals and offers limited testability. In an event where PLL function does not conform to the specifications, it is often hard and time consuming to debug the problems due to limited accessibility of the internal signals. In this paper we propose a testing structure which uses the existing PLL blocks with minimal additional circuitry thus minimizing the area penalty. The VCO (voltage controlled oscillator) frequency range, VCO gain curve, divider operating range and noise contribution can be determined using the proposed method.