A Pseudo-Differential High-Speed Sensing Scheme for Phase-Change Memory

Abstract

Phase-change memory (PCM) has been thought to be a promising candidate as the storage-class memory (SCM) because of its non-volatility, low cost, and superior scalability. However, long read latency and low sensing margin degrade read performance of PCM. To deal with these issues, a novel pseudo-differential high-speed sensing scheme has been proposed. By isolating the sensing nodes from bit-lines and using a differential latch-type sense amplifier, a high read-sensing speed satisfying a given read access yield has been achieved. The sensing time using the proposed sensing scheme is estimated to be 9 ns, which is as much as 52.6% improvement as compared to the conventional sensing scheme. With the proposed sensing scheme, the read energy per bit is also improved up to 43.7%.