An FPGA-based Random Functional Verification Method for Cache

Abstract

Functional verification is the most difficult and time-consuming step in VLSI design flow, owing to the complexity and scale of chips rapidly increasing. The key problem of VLSI functional verification is improving the efficiency and coverage. For the important component-Cache in the microprocessors, an FPGA-based pseudo-random functional verification method is proposed in this paper. The test bench of this method is synthesizable, and the field programmable gate array (FPGA) emulation process is integrated to improve the efficiency of verification. The functional verification coverage is increased by automatically generating the constraints directed pseudo-random test stimuli. The method is applied in the real chips, and is compared with the pseudo-random software simulation method. The results show that our method is faster by about three orders of magnitude, and find more bugs in the designs.