Embedded core testing using genetic algorithms

Abstract

Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and observability of the core are limited by other cores and the user defined logic surrounding the core. One simple but expensive method to solve this problem is to add a wrapper around each core in the SOC, and shift in/out every bit at the core input, output, and possibly its internal state. An approach to remove part of these wrappers using controllability and observability evaluation via random inputs is proposed at the high level (i.e. no gate-level information needed). To achieve better results than the random input vectors, a genetic algorithm is used in this paper to justify the test patterns provided by the core designer. Several high level benchmarks are experimented and results show that with the test patterns generated by the genetic algorithm, both the wrapper size and the test application time are further reduced, while the fault coverage of each core is improved.