Lower the error floor of LDPC with fixed error pattern

Abstract

This paper presented a FEC scheme with very high performance and high information bit rate. By analyzing the error-floor characteristics of a family of QC (Quasi-Cyclic)-LDPC codes, we design a concatenated code to eliminate this kind of trapping set which caused fixed error pattern. The simulation results have demonst-rated the performance of the novel scheme is efficient. The error floor that we estimate is below 1e-15. This approach can be used on the high speed 100Gp/s communication.