Low-race Split-level Charge-Recycling Pass-transistor Logic (LSCPL) for low power

Abstract

In this paper a novel logic family called Low-race Spilt-level Charge-Recycling Pass-transistor Logic (LSCPL) has been proposed that employs a new output driver. LSCPL has high deriving capability due to separating load from pass transistor logic and has less power consumption and smaller delay compared to previously charge recycling logic. It has an additional benefit of lower sensitivity to signal skew. Using new regenerator in LSCPL leads to complete elimination of controller in the circuit, hence the number of transistors was greatly reduced compared to previous Spilt-level Precharge Differential Logic (SPDL). Improvements in the parameters are confirmed by simulating a two input NAND gate.