{"title":"Parallel GF(2n) Modular Squarers","authors":"Trenton J. Grale, E. Swartzlander","doi":"10.1109/MWSCAS.2019.8884794","DOIUrl":null,"url":null,"abstract":"Operations over polynomial Galois fields GF(2n) are employed in a variety of cryptographic systems, such as elliptic curve cryptography (ECC). These operations include multiplication and reduction with respect to an irreducible polynomial modulus. Fast parallel multipliers can be designed at the cost of higher die area. In addition to modular multiplication, ECC employs modular squaring. Certain properties of GF(2n) polynomials make computation of squares trivial. Modular reduction of these squares can be performed in less time and with less hardware complexity compared to the general multiplication case. In an ECC processor, a dedicated squaring unit can potentially reduce overall latency with minimal hardware cost. A fully parallel polynomial n-bit squarer is presented with O(log2n) latency, which uses lookup tables to store modular reduction terms. It is compared with and evaluated against a polynomial multiplier of similar design.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2019.8884794","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Operations over polynomial Galois fields GF(2n) are employed in a variety of cryptographic systems, such as elliptic curve cryptography (ECC). These operations include multiplication and reduction with respect to an irreducible polynomial modulus. Fast parallel multipliers can be designed at the cost of higher die area. In addition to modular multiplication, ECC employs modular squaring. Certain properties of GF(2n) polynomials make computation of squares trivial. Modular reduction of these squares can be performed in less time and with less hardware complexity compared to the general multiplication case. In an ECC processor, a dedicated squaring unit can potentially reduce overall latency with minimal hardware cost. A fully parallel polynomial n-bit squarer is presented with O(log2n) latency, which uses lookup tables to store modular reduction terms. It is compared with and evaluated against a polynomial multiplier of similar design.