System level analysis and benchmarking of graphene interconnects for low-power applications

Abstract

Stochastic wiring distribution models are used to predict the improvement in energy obtained by replacing a few or all copper metal levels with graphene nanoribbons (GNRs) in a low-power digital circuit. The models developed here also estimate the degradation in the performance by replacing a few or all copper metal levels with GNRs. Replacing a few local copper interconnect levels with GNRs is expected to reduce the energy consumed by local interconnects, without severely degrading the performance of longer global interconnects. The hybrid GNR+copper interconnect is shown to perform worse compared to the all GNR interconnect, if the length of the GNR segment is greater than a critical value. For a logic circuit with 30k gates, it is shown that the hybrid interconnect offers a 30 to 40% decrease in energy and a 4× decrease in maximum frequency, whereas the all GNR interconnect offers a 50 to 60% decrease in energy and a 7× decrease in maximum frequency. Further, the impact of edge doping on the resistance per unit length of graphene is analyzed.