Pub Date : 2014-11-20DOI: 10.1109/ISEMC.2014.6899080
P. Triverio
Dispersion relations with filtering were recently proposed to reliably test the causality of sampled scattering parameters obtained with a direct measurement or a full-wave simulation. Owing to the use of a simple low-pass filter, this novel form of relations is much easier to implement and understand than previous approaches. In this paper, we demonstrate, through a rigorous theoretical analysis and numerical tests, that the novel method provides a better estimation of the detected violation. The proposed analysis also elucidates the effect of the low-pass filter on the causality test.
{"title":"An accurate, robust and intuitive technique to detect causality violations in broadband frequency measurements","authors":"P. Triverio","doi":"10.1109/ISEMC.2014.6899080","DOIUrl":"https://doi.org/10.1109/ISEMC.2014.6899080","url":null,"abstract":"Dispersion relations with filtering were recently proposed to reliably test the causality of sampled scattering parameters obtained with a direct measurement or a full-wave simulation. Owing to the use of a simple low-pass filter, this novel form of relations is much easier to implement and understand than previous approaches. In this paper, we demonstrate, through a rigorous theoretical analysis and numerical tests, that the novel method provides a better estimation of the detected violation. The proposed analysis also elucidates the effect of the low-pass filter on the causality test.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117248724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-20DOI: 10.1109/ISEMC.2014.6898934
Dongsheng Zhao, G. Teunisse, F. Leferink
To meet the requirement of doing periodic inter-laboratory verification and self assessment, a device so called reference source is crucial. In this paper, an existing conducted emission reference source is reviewed and a new design is proposed. The considerations are explained, preliminary results are presented thereupon, and the benefits of the design are emphasized in the conclusion.
{"title":"Design and implementation of conducted emission reference source","authors":"Dongsheng Zhao, G. Teunisse, F. Leferink","doi":"10.1109/ISEMC.2014.6898934","DOIUrl":"https://doi.org/10.1109/ISEMC.2014.6898934","url":null,"abstract":"To meet the requirement of doing periodic inter-laboratory verification and self assessment, a device so called reference source is crucial. In this paper, an existing conducted emission reference source is reviewed and a new design is proposed. The considerations are explained, preliminary results are presented thereupon, and the benefits of the design are emphasized in the conclusion.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125957546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-20DOI: 10.1109/ISEMC.2014.6898964
Jonghoon J. Kim, Hongseok Kim, C. Song, In-Myoung Kim, Young-il Kim, Joungho Kim
Wireless power transfer (WPT) technology is becoming increasingly popular for wireless charging of mobile phones and electrical vehicles. Because high power energy is transferred via air, however, the problem of electromagnetic radiated emission from WPT systems is expected to be serious. In this paper, an electromagnetic interface (EMI) and radiation from WPT systems are discussed. Three example technologies for suppressing the electromagnetic-field (EMF) noise and EMI noise from WPT systems are presented. EMF noise from different receiving (RX) coil topologies is characterized and an EMF noise suppression technology using a ferromagnetic material and metallic shielding is analyzed. A handheld resonant magnetic coupling charger (HH-RMCC), a WPT system with very low EMI noise, is then introduced. The proposed technologies for suppressing EMF and EMI noise from a WPT system will be helpful to design engineers.
{"title":"Electromagnetic interference and radiation from wireless power transfer systems","authors":"Jonghoon J. Kim, Hongseok Kim, C. Song, In-Myoung Kim, Young-il Kim, Joungho Kim","doi":"10.1109/ISEMC.2014.6898964","DOIUrl":"https://doi.org/10.1109/ISEMC.2014.6898964","url":null,"abstract":"Wireless power transfer (WPT) technology is becoming increasingly popular for wireless charging of mobile phones and electrical vehicles. Because high power energy is transferred via air, however, the problem of electromagnetic radiated emission from WPT systems is expected to be serious. In this paper, an electromagnetic interface (EMI) and radiation from WPT systems are discussed. Three example technologies for suppressing the electromagnetic-field (EMF) noise and EMI noise from WPT systems are presented. EMF noise from different receiving (RX) coil topologies is characterized and an EMF noise suppression technology using a ferromagnetic material and metallic shielding is analyzed. A handheld resonant magnetic coupling charger (HH-RMCC), a WPT system with very low EMI noise, is then introduced. The proposed technologies for suppressing EMF and EMI noise from a WPT system will be helpful to design engineers.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126067782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-20DOI: 10.1109/ISEMC.2014.6899076
G. Gradoni, T. Antonsen, S. Anlage, E. Ott
An analogy is made between indoor wireless channels and lossy irregular cavities, for which a statistical physics perspective is more appropriate. A statistical model (the Random Coupling Model) for describing the coupling in and out of irregular cavities is used to study the field fluctuations in interconnected environments. It is imagined that the coupling between environments is established by apertures. Monte Carlo simulations are presented for the transfer function between terminals operating in two- and three-cavity chains. The theory confirms numerical and experimental observations of other investigators on nested reverberation chambers. In particular, it is argued that linear chains of N interconnected enclosures can emulate a N-Rayleigh scattering process. Results are of interest for creating laboratory fading channels beyond isolated electromagnetic environments.
{"title":"Random Coupling Model for interconnected wireless environments","authors":"G. Gradoni, T. Antonsen, S. Anlage, E. Ott","doi":"10.1109/ISEMC.2014.6899076","DOIUrl":"https://doi.org/10.1109/ISEMC.2014.6899076","url":null,"abstract":"An analogy is made between indoor wireless channels and lossy irregular cavities, for which a statistical physics perspective is more appropriate. A statistical model (the Random Coupling Model) for describing the coupling in and out of irregular cavities is used to study the field fluctuations in interconnected environments. It is imagined that the coupling between environments is established by apertures. Monte Carlo simulations are presented for the transfer function between terminals operating in two- and three-cavity chains. The theory confirms numerical and experimental observations of other investigators on nested reverberation chambers. In particular, it is argued that linear chains of N interconnected enclosures can emulate a N-Rayleigh scattering process. Results are of interest for creating laboratory fading channels beyond isolated electromagnetic environments.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"136 4 Pt 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123693310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-20DOI: 10.1109/ISEMC.2014.6899081
M. Lai, K. Srinivasan, R. Chakraborty, Madhumita Seshadhri
Assessing the I/O performance delta between dual-referencing and ground-referencing schemes is needed to enable a lower layer count on either board or package, thereby reducing the overall platform cost. Existing methodologies attempted in quantifying impact simultaneously on both PI (Power Integrity) and SI (Signal Integrity) [1], [2] although the work is usually focused on I/O power delivery impact and rarely on actually quantifying impact of different referencing schemes [1]. An initial comparison between different referencing schemes on PKG (package) and BRD (board) has been performed. Then a further analysis has been performed to characterize a PKG with Dual referencing and VSS-Referencing.
{"title":"SI-PI cosimulation analysis of dual referencing and VSS-Referencing memory bus","authors":"M. Lai, K. Srinivasan, R. Chakraborty, Madhumita Seshadhri","doi":"10.1109/ISEMC.2014.6899081","DOIUrl":"https://doi.org/10.1109/ISEMC.2014.6899081","url":null,"abstract":"Assessing the I/O performance delta between dual-referencing and ground-referencing schemes is needed to enable a lower layer count on either board or package, thereby reducing the overall platform cost. Existing methodologies attempted in quantifying impact simultaneously on both PI (Power Integrity) and SI (Signal Integrity) [1], [2] although the work is usually focused on I/O power delivery impact and rarely on actually quantifying impact of different referencing schemes [1]. An initial comparison between different referencing schemes on PKG (package) and BRD (board) has been performed. Then a further analysis has been performed to characterize a PKG with Dual referencing and VSS-Referencing.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122544319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-20DOI: 10.1109/ISEMC.2014.6898963
Dawei Li, Xin Huang, Ji Chen, W. Kainz
Implantable stents can be used as radiation antennas for wireless communication of cardiovascular health monitoring data. However, such stent can also lead to RF induced heating during MRI procedure. In this paper, we investigate the effect of different stent size on the antenna radiation performance as well as its RF induced heating during MRI procedure. Preliminary investigations show that longer stent typically yields to better radiation efficiency but suffers from higher temperature rises.
{"title":"A study of antenna efficiency and MRI compatibility of cardiac stent","authors":"Dawei Li, Xin Huang, Ji Chen, W. Kainz","doi":"10.1109/ISEMC.2014.6898963","DOIUrl":"https://doi.org/10.1109/ISEMC.2014.6898963","url":null,"abstract":"Implantable stents can be used as radiation antennas for wireless communication of cardiovascular health monitoring data. However, such stent can also lead to RF induced heating during MRI procedure. In this paper, we investigate the effect of different stent size on the antenna radiation performance as well as its RF induced heating during MRI procedure. Preliminary investigations show that longer stent typically yields to better radiation efficiency but suffers from higher temperature rises.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129776987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-20DOI: 10.1109/ISEMC.2014.6899070
J. Balasch, Benedikt Gierlichs, Kimmo Jaurvinen, I. Verbauwhede
Many electronic applications use cryptographic algorithms implemented in embedded devices to provide some form of security, e.g. smart cards (banking, SIM, access control), mobile phones, wifi routers, etc. The tight resource constraints of the devices, typically silicon area and power or energy, together with requirements from the application, typically latency or throughput, demand highly efficient implementations of the often computationally complex cryptographic algorithms. We provide a broad overview of the hardware/software co-design space for an essential component of many cryptographic protocols. Based on our experience from teaching a master level course about hardware/software co-design, we explore four typical implementation options and provide concrete implementation results. In addition to the aforementioned criteria, resistance against implementation attacks is vital for the security of embedded cryptographic devices. We analyze our four implementations with respect to a security issue that is due to their electromagnetic emanations, and highlight multiple vulnerabilities that can be exploited to break their security. Next, we investigate state-of-the-art implementation options that are supposed to resist these attacks. We detail their implementation cost and show that it is non-trivial to implement these options securely. Our main contribution is a comprehensive analysis of many implementation options with respect to implementation cost and attack resistance on a single common platform.
{"title":"Hardware/software co-design flavors of elliptic curve scalar multiplication","authors":"J. Balasch, Benedikt Gierlichs, Kimmo Jaurvinen, I. Verbauwhede","doi":"10.1109/ISEMC.2014.6899070","DOIUrl":"https://doi.org/10.1109/ISEMC.2014.6899070","url":null,"abstract":"Many electronic applications use cryptographic algorithms implemented in embedded devices to provide some form of security, e.g. smart cards (banking, SIM, access control), mobile phones, wifi routers, etc. The tight resource constraints of the devices, typically silicon area and power or energy, together with requirements from the application, typically latency or throughput, demand highly efficient implementations of the often computationally complex cryptographic algorithms. We provide a broad overview of the hardware/software co-design space for an essential component of many cryptographic protocols. Based on our experience from teaching a master level course about hardware/software co-design, we explore four typical implementation options and provide concrete implementation results. In addition to the aforementioned criteria, resistance against implementation attacks is vital for the security of embedded cryptographic devices. We analyze our four implementations with respect to a security issue that is due to their electromagnetic emanations, and highlight multiple vulnerabilities that can be exploited to break their security. Next, we investigate state-of-the-art implementation options that are supposed to resist these attacks. We detail their implementation cost and show that it is non-trivial to implement these options securely. Our main contribution is a comprehensive analysis of many implementation options with respect to implementation cost and attack resistance on a single common platform.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126707460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-20DOI: 10.1109/ISEMC.2014.6899046
L. Lo, B. E. Cheah
This paper analyzes the electrical performance of standard and coreless packages up-to 100Gbps data rate. The impact of package design attributes e.g. substrate core thickness, plated through hole (PTH) pad dimension and geometry of second level interconnect (SLI) on insertion loss performance are explored in this study. This study also evaluates the electrical performance of an alternative coreless package solution with metal grid array (MGA) SLI to enable ultra-thin and small form factor electronic devices. In addition to the advantages of configurable and scalable SLI geometry, the full-wave electromagnetic simulation results shows significant insertion loss performance improvement with MGA coreless package as the frequency increases. The root-causes of insertion loss degradations among the evaluated packaging solutions were identified and further discussed in this paper.
{"title":"Package technology evaluation and optimization for high-speed applications","authors":"L. Lo, B. E. Cheah","doi":"10.1109/ISEMC.2014.6899046","DOIUrl":"https://doi.org/10.1109/ISEMC.2014.6899046","url":null,"abstract":"This paper analyzes the electrical performance of standard and coreless packages up-to 100Gbps data rate. The impact of package design attributes e.g. substrate core thickness, plated through hole (PTH) pad dimension and geometry of second level interconnect (SLI) on insertion loss performance are explored in this study. This study also evaluates the electrical performance of an alternative coreless package solution with metal grid array (MGA) SLI to enable ultra-thin and small form factor electronic devices. In addition to the advantages of configurable and scalable SLI geometry, the full-wave electromagnetic simulation results shows significant insertion loss performance improvement with MGA coreless package as the frequency increases. The root-causes of insertion loss degradations among the evaluated packaging solutions were identified and further discussed in this paper.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123999859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-20DOI: 10.1109/ISEMC.2014.6899084
K. Shringarpure, Biyao Zhao, B. Archambeault, A. Ruehli, J. Fan, J. Drewniak
The printed circuit board (PCB) power delivery network (PDN) performance has become critical with the reducing margins on power noise. This paper deals with a specific question about the size of the power area fill used to route the power current from the dc regulator to integrated circuit(IC), and also used for connecting to the decoupling capacitors. With increased PCB real estate costs, narrow power fills are required, which results in an increase in the connection inductance of decoupling capacitors. This paper uses a proven lumped circuit model extraction procedure, based on the first principle resonant cavity model, to demonstrate the effect of narrow and wide area fills used in typical PCB PDN designs. The frequency domain results thus obtained are used with typical IC current draw profiles to show the impact on the noise voltage developed at the IC. Some design guidelines and conclusions are drawn from these results.
{"title":"Effect of narrow power fills on PCB PDN noise","authors":"K. Shringarpure, Biyao Zhao, B. Archambeault, A. Ruehli, J. Fan, J. Drewniak","doi":"10.1109/ISEMC.2014.6899084","DOIUrl":"https://doi.org/10.1109/ISEMC.2014.6899084","url":null,"abstract":"The printed circuit board (PCB) power delivery network (PDN) performance has become critical with the reducing margins on power noise. This paper deals with a specific question about the size of the power area fill used to route the power current from the dc regulator to integrated circuit(IC), and also used for connecting to the decoupling capacitors. With increased PCB real estate costs, narrow power fills are required, which results in an increase in the connection inductance of decoupling capacitors. This paper uses a proven lumped circuit model extraction procedure, based on the first principle resonant cavity model, to demonstrate the effect of narrow and wide area fills used in typical PCB PDN designs. The frequency domain results thus obtained are used with typical IC current draw profiles to show the impact on the noise voltage developed at the IC. Some design guidelines and conclusions are drawn from these results.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123676101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-20DOI: 10.1109/ISEMC.2014.6898944
F. Rao, S. Hindi
Effects of transmit jitter on lossy clock channel are analyzed analytically by treating the 1010 input clock signal as a sinusoidal wave with a phase modulation that represents jitter. Jitter-to-amplitude-modulation transfer functions are derived for sinusoidal jitter and random jitter in terms of the signal transfer function or S-parameters. Input jitter is shown to induce amplitude modulation in the output signal as a result of channel dispersion, leading to voltage noise at the channel output. RJ induced voltage noise is found to scale uniquely with channel loss. To verify the theory, numerical simulations are performed on channels with different losses and at various data rates. The input clock signal is represented with a square wave, and the output signal is calculated by linear superposition of the channel step response. Theoretical and simulation results are found to be in excellent agreement.
{"title":"Jitter induced voltage noise in clock channels","authors":"F. Rao, S. Hindi","doi":"10.1109/ISEMC.2014.6898944","DOIUrl":"https://doi.org/10.1109/ISEMC.2014.6898944","url":null,"abstract":"Effects of transmit jitter on lossy clock channel are analyzed analytically by treating the 1010 input clock signal as a sinusoidal wave with a phase modulation that represents jitter. Jitter-to-amplitude-modulation transfer functions are derived for sinusoidal jitter and random jitter in terms of the signal transfer function or S-parameters. Input jitter is shown to induce amplitude modulation in the output signal as a result of channel dispersion, leading to voltage noise at the channel output. RJ induced voltage noise is found to scale uniquely with channel loss. To verify the theory, numerical simulations are performed on channels with different losses and at various data rates. The input clock signal is represented with a square wave, and the output signal is calculated by linear superposition of the channel step response. Theoretical and simulation results are found to be in excellent agreement.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116354277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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