An improved test control architecture and test control expansion for core-based system chips

Abstract

Abstract This paper presents improvement of a core-based chip™s test control architecture that uses Std IEEE 1149.1 TAP to access core level register Test Control Blocks (TCB). We show enhancements for the register TCB, to improve its test coverage, to enable IEEE 1149.1 compliant RUNBIST and to optimize chip level TCB access. In addition, Test Control Expansion (TCE) is presented. TCE automatically validates test control architecture in a design netlist, and is capable of calculating chip level test mode initialization sequences. 1. Introduction ‚Divide and conquer™, a well-known strategy that was born in ancient times. Needless to say that it is still alive and an absolute must in today™s system chip design. Modern system chips are built by merging IP cores, which are often delivered from several companies. Each core providing company focuses on their own expertise. This enables the development of innovative, high quality products in reasonable time. Given the amount of resources active in the design domain, multiple cores can be developed in the same time frame. These cores find their way into multiple designs, serving a variety of application areas. The ease of merging IP delivered from more than one source, heavily correlates with the availability of a robust re-use strategy. Such a strategy leads to ‚conquer™ by not only ‚divide™ in the functional domain, but in the test domain as well. For this reason the IEEE P1500 Working Group [13] pursues a standard for testing embedded cores. It tries to define a standard that facilitates the test interoperability of IP cores from different sources. Ideally this results in a ‚plug & play™ environment in which tests delivered with a core can be executed, without modifications, even when this core is deeply embedded in a large system chip. The conceptual architecture for testing embedded cores in system chips, consists of a pattern source and sink, a test access mechanism and a core test wrapper [4]. These elements are often discussed in relation with test data reduction, test time optimization and test scheduling. In this paper we deal with the accompanying test control. We present a test control concept that makes use of hardware structures, similar to the TCB defined by the Virtual Socket Interface Alliance (VSIA). This test control hardware also can be seen as a subset of the IEEE P1500 Wrapper Instruction Register (WIR). Besides improvement and new features in hardware we introduce a unique tool flow that is currently used to generate, and efficiently evaluate, test control for large system chips. The sequel of this paper is organized as follows. Section 2 gives an overview of prior work done in the domain of test control hardware. Section 2.1 introduces the Philips Test Control Architecture. In section 3 features are presented that improve the test coverage of both TCB and the logic it controls. It also describes a mechanism to implement test control for the standard IEEE 1149.1 runbist instruction. This section also presents an optimization feature for chip level Test Control access. Section 4 presents Test Control Expansion. This is a process that translates core level TCB initializations to chip level. Section 5 concludes this paper.