Short channel effects (SCEs) characterization of underlaped dual-K spacer in dual-metal gate FinFET device

Abstract

FinFETs are new structures for scaling the devices at sub-nanometer regime to continue the Moore's law. To increase the performance of FinFETs, a dual metal gate with underlap concepts has been introduced. Moreover, its performance can be enhanced by spacers. The dual metal gate comprises of two different workfunction materials (Molybdenum and Tungsten) for double gate (DG) and triple gate (TG) FinFET structures with different underlap length (LUN) has been presented. The TG FinFET exhibits the better control of short channel effects (SCEs) over the DG FinFET device. The significance of the spacer with a variation of spacer length poses the use of dual-k spacer in TG FinFET device to procure the better performance such as high on-current (Ion), Ion/Ioff ratio and smaller subthreshold swing (SS), drain induced barrier lowering (DIBL). The simulation carried by SILVACO ATLAS, and it shows that TG FinFET with different combination of dual-k (smaller high-k length (Lhk), larger low-k length (Llk)) draws an attention for nanoscale application.