Yang Xu, Praveen Kumar Venkatachala, Spencer Leuenberger, U. Moon
{"title":"A 7.5mW 35–70MHz 4th-order semi-passive charge-sharing band-pass filter with programmable bandwidth and 72dB stop-band rejection in 65nm CMOS","authors":"Yang Xu, Praveen Kumar Venkatachala, Spencer Leuenberger, U. Moon","doi":"10.1109/RFIC.2016.7508276","DOIUrl":null,"url":null,"abstract":"This paper proposes a highly reconfigurable charge-domain switched-gm-C biquad band-pass filter (BPF) topology that uses a semi-passive charge-sharing technique. It uses only switches, capacitors, digital circuitry for 3-phase non-overlapping clock generation and linearity-enhanced gm-stages. A 4th-order BPF prototype operating at 1.2GS/s sampling rate is implemented using a cascade of two independent biquads in a 65nm LPE CMOS. A tunable center frequency of 35-70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The in-band 1-dB compression point is -2.4dBm, and the in-band IIP3 is +9dBm. The filter prototype consumes 7.5mW from a 1.2V supply, and occupies an active area of 0.17mm2.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"227 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2016.7508276","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper proposes a highly reconfigurable charge-domain switched-gm-C biquad band-pass filter (BPF) topology that uses a semi-passive charge-sharing technique. It uses only switches, capacitors, digital circuitry for 3-phase non-overlapping clock generation and linearity-enhanced gm-stages. A 4th-order BPF prototype operating at 1.2GS/s sampling rate is implemented using a cascade of two independent biquads in a 65nm LPE CMOS. A tunable center frequency of 35-70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The in-band 1-dB compression point is -2.4dBm, and the in-band IIP3 is +9dBm. The filter prototype consumes 7.5mW from a 1.2V supply, and occupies an active area of 0.17mm2.
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