Pub Date : 2016-05-23DOI: 10.1109/RFIC.2016.7508297
Hugo Westerveld, E. Klumperink, B. Nauta
With the growing amount of wireless devices, interference robustness is a receiver specification of increasing importance. This paper presents a technique that improves both out-of-band compression and weakly non-linear distortion. It mitigates the effect of non-linearity in the baseband amplifier by preceding it by a cross-coupled passive filter. This provides a highly linear passive shunt path for out-of-band currents, while maintaining wideband input matching. The 65nm CMOS prototype chip achieves 41dBm out-of-band IIP3 at 40MHz offset and an 11dBm out-of-band blocker compression point. The chip has an area of 0.8mm2 and consumes 46mW from a 1.2V supply.
{"title":"A cross-coupled switch-RC mixer-first technique achieving +41dBm out-of-band IIP3","authors":"Hugo Westerveld, E. Klumperink, B. Nauta","doi":"10.1109/RFIC.2016.7508297","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508297","url":null,"abstract":"With the growing amount of wireless devices, interference robustness is a receiver specification of increasing importance. This paper presents a technique that improves both out-of-band compression and weakly non-linear distortion. It mitigates the effect of non-linearity in the baseband amplifier by preceding it by a cross-coupled passive filter. This provides a highly linear passive shunt path for out-of-band currents, while maintaining wideband input matching. The 65nm CMOS prototype chip achieves 41dBm out-of-band IIP3 at 40MHz offset and an 11dBm out-of-band blocker compression point. The chip has an area of 0.8mm2 and consumes 46mW from a 1.2V supply.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116667887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508300
Varish Diddi, Shuichi Sakata, S. Shinjo, Voravit Vorapipat, R. Eden, P. Asbeck
A multiWatt RF power amplifier operating in the frequency range 0.5 to 1.2 GHz is reported, whose output amplitude is determined by digital input words (“RF Power DAC operation”). The amplifier employs a CMOS IC for digital control, directly connected to a GaN FET operating in common-gate mode. The use of the GaN FET allows power supply voltages in excess of 15 V to be used. A load resistance of 50 ohms can be directly connected to the GaN FET, thereby avoiding bandwidth limitations from output matching networks. Output power in the range 2 to 3 W and drain efficiencies above 50% are obtained over more than an octave of bandwidth.
{"title":"Broadband digitally-controlled power amplifier based on CMOS / GaN combination","authors":"Varish Diddi, Shuichi Sakata, S. Shinjo, Voravit Vorapipat, R. Eden, P. Asbeck","doi":"10.1109/RFIC.2016.7508300","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508300","url":null,"abstract":"A multiWatt RF power amplifier operating in the frequency range 0.5 to 1.2 GHz is reported, whose output amplitude is determined by digital input words (“RF Power DAC operation”). The amplifier employs a CMOS IC for digital control, directly connected to a GaN FET operating in common-gate mode. The use of the GaN FET allows power supply voltages in excess of 15 V to be used. A load resistance of 50 ohms can be directly connected to the GaN FET, thereby avoiding bandwidth limitations from output matching networks. Output power in the range 2 to 3 W and drain efficiencies above 50% are obtained over more than an octave of bandwidth.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114988816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508319
J. van Sinderen, L. Breems, H. Brekelmans, Frank Leong, N. Pavlovic, R. Rutten, J. Niehof, R. Roovers, Bernard Burdiek, J. Rudolph, Ulrich Möhlmann, Peter Blinzer, M. Biehl, N. Gabriel, Andreas Wichern, G. Schippmann, Frank Rethmeier, J. Klimczak, Joerg Wenzel, R. Pilaski
This paper describes a single-PLL, fixed-oscillator, wide-band multi-tuner HD Radio & DAB/T-DMB receiver for concurrent multi-band & multi-channel car radio reception, fully integrated in a 65nm CMOS SoC. Besides saving area and power for the LO and clock generation, the presented architecture also prevents oscillator pulling and spurs. Harmonic rejection mixers have been used to suppress down-conversion with LO harmonics up to 60dB, which reduces the required amount of RF filtering. The DAB measurement results show best-in-class blocker performance (FoS up to 70dBc) in combination with state-of-the-art sensitivity down to -102dBm.
{"title":"A wideband single-PLL RF receiver for simultaneous multi-band and multi-channel digital car Radio reception","authors":"J. van Sinderen, L. Breems, H. Brekelmans, Frank Leong, N. Pavlovic, R. Rutten, J. Niehof, R. Roovers, Bernard Burdiek, J. Rudolph, Ulrich Möhlmann, Peter Blinzer, M. Biehl, N. Gabriel, Andreas Wichern, G. Schippmann, Frank Rethmeier, J. Klimczak, Joerg Wenzel, R. Pilaski","doi":"10.1109/RFIC.2016.7508319","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508319","url":null,"abstract":"This paper describes a single-PLL, fixed-oscillator, wide-band multi-tuner HD Radio & DAB/T-DMB receiver for concurrent multi-band & multi-channel car radio reception, fully integrated in a 65nm CMOS SoC. Besides saving area and power for the LO and clock generation, the presented architecture also prevents oscillator pulling and spurs. Harmonic rejection mixers have been used to suppress down-conversion with LO harmonics up to 60dB, which reduces the required amount of RF filtering. The DAB measurement results show best-in-class blocker performance (FoS up to 70dBc) in combination with state-of-the-art sensitivity down to -102dBm.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120943944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508292
R. Guerra, A. Finocchiaro, G. Papotto, B. Messina, Leandro Grasso, R. La Rosa, G. Zoppi, Giuseppe Notarangelo, G. Palmisano
A fully integrated RF-powered receiver for remotely controlled systems is presented. The receiver adopts ASK and FSK modulations and is capable of operating in the ISM bands of 433 MHz, 869 MHz, and 915 MHz, while achieving a bit rate down to 62 kb/s. The circuit includes an RF harvester and a power management unit for the RF to DC power conversion and control, respectively, and an OTP memory with a digital interface for the operating configuration. Measurements show a harvester sensitivity of -18.8 dBm and accurate ASK demodulation with a modulation index as low as 10%. The current consumption is 87 μA and 720 μA for the ASK and FSK receiving mode, respectively. The circuit was fabricated in a 0.13-μm CMOS technology and occupies a core area of 2.2 mm2.
{"title":"An RF-powered FSK/ASK receiver for remotely controlled systems","authors":"R. Guerra, A. Finocchiaro, G. Papotto, B. Messina, Leandro Grasso, R. La Rosa, G. Zoppi, Giuseppe Notarangelo, G. Palmisano","doi":"10.1109/RFIC.2016.7508292","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508292","url":null,"abstract":"A fully integrated RF-powered receiver for remotely controlled systems is presented. The receiver adopts ASK and FSK modulations and is capable of operating in the ISM bands of 433 MHz, 869 MHz, and 915 MHz, while achieving a bit rate down to 62 kb/s. The circuit includes an RF harvester and a power management unit for the RF to DC power conversion and control, respectively, and an OTP memory with a digital interface for the operating configuration. Measurements show a harvester sensitivity of -18.8 dBm and accurate ASK demodulation with a modulation index as low as 10%. The current consumption is 87 μA and 720 μA for the ASK and FSK receiving mode, respectively. The circuit was fabricated in a 0.13-μm CMOS technology and occupies a core area of 2.2 mm2.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128789819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508305
Neha Sinha, Mansour Rachid, S. Pamarti
A 65nm CMOS, 8mW spectrum scanner using simple but linear periodically time-varying (LPTV) circuits is presented. The scanner spans a 1GHz spectrum by providing sharp filters at programmable centre frequencies. Its passive structure gives it a measured out-of-band IIP3 of > +31dBm and a sensitivity of <; -142dBm/Hz across the 1GHz band leading to an SFDR of 75dB in a 1MHz resolution bandwidth.
{"title":"An 8mW, 1GHz span, passive spectrum scanner with > +31dBm out-of-band IIP3","authors":"Neha Sinha, Mansour Rachid, S. Pamarti","doi":"10.1109/RFIC.2016.7508305","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508305","url":null,"abstract":"A 65nm CMOS, 8mW spectrum scanner using simple but linear periodically time-varying (LPTV) circuits is presented. The scanner spans a 1GHz spectrum by providing sharp filters at programmable centre frequencies. Its passive structure gives it a measured out-of-band IIP3 of > +31dBm and a sensitivity of <; -142dBm/Hz across the 1GHz band leading to an SFDR of 75dB in a 1MHz resolution bandwidth.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128711435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508256
Chuan Qin, Lei Zhang, Zhijian Pan, Li Zhang, Yan Wang, Zhiping Yu
In this paper, a novel receiver architecture with inductor-noise cancellation technique is presented. The proposed receiver employs two separate down-conversion paths driven by I/Q LOs respectively, and the noise of on-chip gate inductor of common-source LNA is cancelled at the baseband output, without additional penalty on power consumption, while the signal is in-phase and strengthened. The noise figure is therefore significantly improved versus prior arts. A demo 5-GHz receiver employing the proposed architecture is designed and implemented in a 65-nm low power CMOS process. Measured result shows a noise figure of 1.8 dB at 5 GHz band, while consuming only 95 mW of power from a 1.2 V supply.
{"title":"A 5-GHz inductor-noise cancelling receiver with 1.8 dB noise figure in 65nm LP CMOS","authors":"Chuan Qin, Lei Zhang, Zhijian Pan, Li Zhang, Yan Wang, Zhiping Yu","doi":"10.1109/RFIC.2016.7508256","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508256","url":null,"abstract":"In this paper, a novel receiver architecture with inductor-noise cancellation technique is presented. The proposed receiver employs two separate down-conversion paths driven by I/Q LOs respectively, and the noise of on-chip gate inductor of common-source LNA is cancelled at the baseband output, without additional penalty on power consumption, while the signal is in-phase and strengthened. The noise figure is therefore significantly improved versus prior arts. A demo 5-GHz receiver employing the proposed architecture is designed and implemented in a 65-nm low power CMOS process. Measured result shows a noise figure of 1.8 dB at 5 GHz band, while consuming only 95 mW of power from a 1.2 V supply.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132949866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508246
B. Sheinman, E. Bloch, N. Mazor, Run Levinger, R. Ben-Yishay, O. Katz, R. Carmon, A. Golberg, J. Vovnoboy, A. Bruetbart, M. Rachman, D. Elad
A fully integrated 60 GHz transmitter in 130 nm BiCMOS SiGe technology for outdoor applications is presented. The transmitter covers the entire 57-66 GHz band supporting a record data rate of 16.2 Gbps at 6 dBm output power, 512 QAM with an EVM of -34 dB. The single ended saturated power, OP1dB, and OIP3 are above 18 dBm, 16 dBm and 23 dBm respectively. The transmitter meets the most stringent ETSI emission mask for point-to-point communication at class6LB, 500 MHz bandwidth with an output noise floor below -133 dBm/Hz. The area of the transmitter is 15 mm2 and it consumes 1.2 W.
{"title":"A 16.2 Gbps 60 GHz SiGe transmitter for outdoor wireless links","authors":"B. Sheinman, E. Bloch, N. Mazor, Run Levinger, R. Ben-Yishay, O. Katz, R. Carmon, A. Golberg, J. Vovnoboy, A. Bruetbart, M. Rachman, D. Elad","doi":"10.1109/RFIC.2016.7508246","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508246","url":null,"abstract":"A fully integrated 60 GHz transmitter in 130 nm BiCMOS SiGe technology for outdoor applications is presented. The transmitter covers the entire 57-66 GHz band supporting a record data rate of 16.2 Gbps at 6 dBm output power, 512 QAM with an EVM of -34 dB. The single ended saturated power, OP1dB, and OIP3 are above 18 dBm, 16 dBm and 23 dBm respectively. The transmitter meets the most stringent ETSI emission mask for point-to-point communication at class6LB, 500 MHz bandwidth with an output noise floor below -133 dBm/Hz. The area of the transmitter is 15 mm2 and it consumes 1.2 W.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132699706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508296
Esmail Babakrpur, W. Namgoong
This paper presents a blocker tolerant low-noise wideband receiver that employs digital harmonic rejection equalizer to suppress high order harmonic interferers. Unlike the commonly employed 8-phase harmonic rejection mixers (HRMs), the proposed wideband receiver suppresses any of the harmonic interferers including the seventh and ninth. The wideband receiver employs a two-path front-end structure, consisting of a highly linear mixer-first primary path and gm-first secondary path. An adaptive minimum mean-squared error (MMSE) harmonic rejection equalizer is employed that minimizes the desired signal distortion in the mean-squared error sense in the presence of arbitrary harmonic interferers and the correlated noise between the two paths. Using two sets of 4-phase clocks, a 100-1450MHz receiver that achieves HRR >75dB up to the ninth harmonic while being robust to mismatches is implemented.
{"title":"A 4-phase blocker tolerant wideband receiver with MMSE harmonic rejection equalizer","authors":"Esmail Babakrpur, W. Namgoong","doi":"10.1109/RFIC.2016.7508296","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508296","url":null,"abstract":"This paper presents a blocker tolerant low-noise wideband receiver that employs digital harmonic rejection equalizer to suppress high order harmonic interferers. Unlike the commonly employed 8-phase harmonic rejection mixers (HRMs), the proposed wideband receiver suppresses any of the harmonic interferers including the seventh and ninth. The wideband receiver employs a two-path front-end structure, consisting of a highly linear mixer-first primary path and gm-first secondary path. An adaptive minimum mean-squared error (MMSE) harmonic rejection equalizer is employed that minimizes the desired signal distortion in the mean-squared error sense in the presence of arbitrary harmonic interferers and the correlated noise between the two paths. Using two sets of 4-phase clocks, a 100-1450MHz receiver that achieves HRR >75dB up to the ninth harmonic while being robust to mismatches is implemented.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114305272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508317
Ying Chen, M. van der Heijden, D. Leenaerts
This paper demonstrates a 1-Watt output power amplifier MMIC operating from 13.5GHz to 14.5GHz (Ku-band). The power amplifier employs an on-chip integrated 16-way in-phase output current combiner to achieve the required output power. Implemented in a 0.25-μm SiGe:C BiCMOS technology, the power amplifier achieves a power-added efficiency of 37.5% at 14.1GHz with greater than 35.5% across the band of interest.
{"title":"A 1-Watt Ku-band power amplifier in SiGe with 37.5% PAE","authors":"Ying Chen, M. van der Heijden, D. Leenaerts","doi":"10.1109/RFIC.2016.7508317","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508317","url":null,"abstract":"This paper demonstrates a 1-Watt output power amplifier MMIC operating from 13.5GHz to 14.5GHz (Ku-band). The power amplifier employs an on-chip integrated 16-way in-phase output current combiner to achieve the required output power. Implemented in a 0.25-μm SiGe:C BiCMOS technology, the power amplifier achieves a power-added efficiency of 37.5% at 14.1GHz with greater than 35.5% across the band of interest.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115108650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508279
S. Spiridon, D. Koh, J. Xiao, M. Brandolini, B. Shen, C. Hsiao, H. Huang, D. Guermandi, S. Bozzola, H. Yan, M. Introini, L. Krishnan, K. Raviprakash, Y. Shin, R. Gomez, J. Chang
A 28 nm CMOS Software-Defined Transceiver (SDTRX) enabling High-Speed Data (HSD) streaming, including Ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at the lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a DAC-based TX and a smart PLL system. It operates over a 0.4-to-1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple TX-RX loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia SoCs and is, to the authors' knowledge, the first reported transceiver front end to enable true high-speed data streaming within home cable networks.
{"title":"A 28 nm, 475 mW, 0.4-to-1.7 GHz embedded transceiver front-end enabling high-speed data streaming within home cable networks","authors":"S. Spiridon, D. Koh, J. Xiao, M. Brandolini, B. Shen, C. Hsiao, H. Huang, D. Guermandi, S. Bozzola, H. Yan, M. Introini, L. Krishnan, K. Raviprakash, Y. Shin, R. Gomez, J. Chang","doi":"10.1109/RFIC.2016.7508279","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508279","url":null,"abstract":"A 28 nm CMOS Software-Defined Transceiver (SDTRX) enabling High-Speed Data (HSD) streaming, including Ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at the lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a DAC-based TX and a smart PLL system. It operates over a 0.4-to-1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple TX-RX loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia SoCs and is, to the authors' knowledge, the first reported transceiver front end to enable true high-speed data streaming within home cable networks.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116481515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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