A 13.3W 5-Gb/s two-dimensional eye-opening monitor in 40nm CMOS technology

Abstract

This paper presents an eye-opening monitor (EOM) architecture used in the high-speed wireline communication system. Compared with the conventional 2-D EOM, the proposed rectangular 2-D EOM provides variable asymmetric sizes of masks. Single-quadrant phase interpolators (PIs) and independent digital-to-analog converters (DACs) controlled by the external signals generate asymmetric masks. Different masks with the same bit error rate (BER) are overlapped to emerge non-rectangular eye diagram shape. The proposed 2-D EOM is designed in 40 nm CMOS process and operates up to 5 Gb/s data rate at 1.1V power supply. Each PI has 90° variable range with 6° phase step. Meanwhile, each 6 bit DAC generates asymmetric reference voltages compared with the common voltage. So this design provides 1080 different masks to not only improve the accuracy of eye diagram but also detect the offset of data. The total power consumption of the proposed EOM is 13.3mW.