Constant capacity signal flow signal processor architecture benchmark

Abstract

This paper describes the implementation and benchmark testing of a high performance signal processor architecture based on the alternate low level primitive structures (ALPS) concept developed by the Naval Research Laboratory. The research shows that such digital signal processor architectures are not only feasible but provide a modular solution to a wide range of signal processing applications. In addition the benchmark tests show that such architectures provide higher efficiency and lower data transfer network contentions than existing global memory-based data flow architectures. The processor system consists of high-performance, fully programmable, embedded signal processors and controllers networked on a set of high bandwidth busses to provide a processing capability far in excess of that offered by current systems. The modular array processor (MAP) is a networked multiprocessor with VLSI-based signal and control processing modules.<>