Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218556
Mehdi Rahman, D. Meyer
To ensure smooth and accurate movement of a robot arm, the robot inverse dynamics problem must be solved at each servo sampling. The computation of this problem, however, is a mathematically intense task which degrades the sampling period of presentday robot control systems. In addition to the repetitive requirement for its evaluation, the linearly recursive and computer-bound properties of the robot inverse dynamics problem using the Newton-Euler (N-E) equations of motion suggest that it is amenable for direct mapping onto a fixed systolic array structure. This paper presents such an architecture and discusses its implementation in 1-micron CMOS technology, to compute the N-E algorithm for an n-link manipulator, within a period of 69+12n clock cycles. For a six-link robot manipulator operating at the maximum device frequency of 25 MHz, the total execution time is 5.64 mu s. The die size of this robot controller chip is 530*485 square mils, and its estimated power dissipation at the specified frequency is 3.5 watts.<>
{"title":"A systolic array chip for robot inverse dynamics computation","authors":"Mehdi Rahman, D. Meyer","doi":"10.1109/ASAP.1992.218556","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218556","url":null,"abstract":"To ensure smooth and accurate movement of a robot arm, the robot inverse dynamics problem must be solved at each servo sampling. The computation of this problem, however, is a mathematically intense task which degrades the sampling period of presentday robot control systems. In addition to the repetitive requirement for its evaluation, the linearly recursive and computer-bound properties of the robot inverse dynamics problem using the Newton-Euler (N-E) equations of motion suggest that it is amenable for direct mapping onto a fixed systolic array structure. This paper presents such an architecture and discusses its implementation in 1-micron CMOS technology, to compute the N-E algorithm for an n-link manipulator, within a period of 69+12n clock cycles. For a six-link robot manipulator operating at the maximum device frequency of 25 MHz, the total execution time is 5.64 mu s. The die size of this robot controller chip is 530*485 square mils, and its estimated power dissipation at the specified frequency is 3.5 watts.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124866484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218538
Prashanth Kuchibhotla, B. Rao
Various methods for mapping signal processing algorithms into systolic arrays have been developed in the past few years. In this paper, efficient scheduling techniques are developed for the partitioning problem, i.e. problems with size that do not match the array size. In particular, scheduling for the locally parallel-globally sequential (LPGS) technique and the locally sequential-globally parallel (LSGP) technique are developed. The scheduling procedure developed exploits the fact that after LPGS and LSGP partitioning, the locality constraints become modified allowing for more flexibility. The new structure allows the authors to develop a flexible scheduling order for LPGS that is useful in evaluating a trade-off between execution time and size of partitioning buffers. The benefits of the scheduling techniques are illustrated with the help of matrix multiplication and least-squares examples.<>
{"title":"Efficient scheduling methods for partitioned systolic algorithms","authors":"Prashanth Kuchibhotla, B. Rao","doi":"10.1109/ASAP.1992.218538","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218538","url":null,"abstract":"Various methods for mapping signal processing algorithms into systolic arrays have been developed in the past few years. In this paper, efficient scheduling techniques are developed for the partitioning problem, i.e. problems with size that do not match the array size. In particular, scheduling for the locally parallel-globally sequential (LPGS) technique and the locally sequential-globally parallel (LSGP) technique are developed. The scheduling procedure developed exploits the fact that after LPGS and LSGP partitioning, the locality constraints become modified allowing for more flexibility. The new structure allows the authors to develop a flexible scheduling order for LPGS that is useful in evaluating a trade-off between execution time and size of partitioning buffers. The benefits of the scheduling techniques are illustrated with the help of matrix multiplication and least-squares examples.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116740793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218566
Joseph B. Evans, Bede Liu
The implementation of digital signal processing algorithms often requires that a variety of conflicting criteria be satisfied. A signal processing system must provide the necessary processing gains, while various measures of the feasibility and efficiency of implementation, such as power and cost, are met. This paper reviews the motivation behind the development of low power signal processing algorithms, presents some methods for addressing these problems, and gives several examples of reduced complexity signal processing implementations.<>
{"title":"Some low power implementations of DSP algorithms","authors":"Joseph B. Evans, Bede Liu","doi":"10.1109/ASAP.1992.218566","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218566","url":null,"abstract":"The implementation of digital signal processing algorithms often requires that a variety of conflicting criteria be satisfied. A signal processing system must provide the necessary processing gains, while various measures of the feasibility and efficiency of implementation, such as power and cost, are met. This paper reviews the motivation behind the development of low power signal processing algorithms, presents some methods for addressing these problems, and gives several examples of reduced complexity signal processing implementations.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134415804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218561
A. Gunzinger, U. A. Müller, W. Scott, B. Bäumle, P. Kohler, W. Guggenbühl
This paper describes a parallel distributed computer architecture called MUSIC (multi signal processor system with intelligent communication). A single processor element (PE) consists of a DSP 96002 from Motorola (60 MFlops), program and data memory and a fast, independent communication interface; all communication interfaces are connected through a communication ring. A system with 30 processor elements (PEs) is operational. It has a peak performance of 1.8 GFlops, an electrical power consumption of about 350 watt (including forced air cooling). It fits into a 19 inch rack. The hardware price of this system is 40000 US $ which means a selling price of approximately 200000 US $. Beside the wellknown Mandelbrot algorithm (601 MFlops sustained), two real applications are at the moment successfully implemented on the system: the backpropagation algorithm for neural net learning results in a peak performance of 150 MCUPS (million connection updates per second) which equals 900 MFlops sustained and the molecular dynamics simulation program MD-Atom (443 MFlops sustained). Other applications of the system are in digital signal processing and finite element computation.<>
本文介绍了一种并行分布式计算机体系结构MUSIC (multi signal processor system with intelligent communication)。单处理器单元(PE)由摩托罗拉的DSP 96002 (60 MFlops)、程序和数据存储器以及一个快速、独立的通信接口组成;所有通信接口通过通信环连接。一个有30个处理器元素(pe)的系统是可操作的。它的峰值性能为1.8 GFlops，电力消耗约为350瓦(包括强制空气冷却)。它可以放在一个19英寸的架子上。该系统的硬件价格为40000美元，这意味着售价约为200000美元。除了著名的Mandelbrot算法(持续601 MFlops)，目前在系统上成功实现了两个实际应用:用于神经网络学习的反向传播算法的峰值性能为150 MCUPS(每秒百万次连接更新)，相当于持续900 MFlops，以及分子动力学模拟程序MD-Atom(持续443 MFlops)。该系统的其他应用还包括数字信号处理和有限元计算
{"title":"Architecture and realization of a multi signal processor system","authors":"A. Gunzinger, U. A. Müller, W. Scott, B. Bäumle, P. Kohler, W. Guggenbühl","doi":"10.1109/ASAP.1992.218561","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218561","url":null,"abstract":"This paper describes a parallel distributed computer architecture called MUSIC (multi signal processor system with intelligent communication). A single processor element (PE) consists of a DSP 96002 from Motorola (60 MFlops), program and data memory and a fast, independent communication interface; all communication interfaces are connected through a communication ring. A system with 30 processor elements (PEs) is operational. It has a peak performance of 1.8 GFlops, an electrical power consumption of about 350 watt (including forced air cooling). It fits into a 19 inch rack. The hardware price of this system is 40000 US $ which means a selling price of approximately 200000 US $. Beside the wellknown Mandelbrot algorithm (601 MFlops sustained), two real applications are at the moment successfully implemented on the system: the backpropagation algorithm for neural net learning results in a peak performance of 150 MCUPS (million connection updates per second) which equals 900 MFlops sustained and the molecular dynamics simulation program MD-Atom (443 MFlops sustained). Other applications of the system are in digital signal processing and finite element computation.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132966292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218583
A. Darte, L. Khachiyan, Y. Robert
This paper deals with the problem of finding optimal schedulings for uniform dependence algorithms. Given a convex domain, let T/sub f/ be the total time needed to execute all computations using the free (greedy) schedule and let T/sub l/ be the total time needed to execute all computations using the optimal linear schedule. The authors' main result is to bound T/sub l//T/sub f/ and T/sub l/-T/sub f/ for sufficiently 'fat' domains.<>
{"title":"Linear scheduling is close to optimality","authors":"A. Darte, L. Khachiyan, Y. Robert","doi":"10.1109/ASAP.1992.218583","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218583","url":null,"abstract":"This paper deals with the problem of finding optimal schedulings for uniform dependence algorithms. Given a convex domain, let T/sub f/ be the total time needed to execute all computations using the free (greedy) schedule and let T/sub l/ be the total time needed to execute all computations using the optimal linear schedule. The authors' main result is to bound T/sub l//T/sub f/ and T/sub l/-T/sub f/ for sufficiently 'fat' domains.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129610871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218547
A. Mukherjee
This paper presents special-purpose linear array processor architecture for determining longest common subsequences (LCS) of two sequences. The algorithm uses systolic and pipelined architectures suitable for VLSI implementation. The algorithms are also suitable for implementation on parallel machines. The author first develops a 'greedy' algorithm to determine some of the LCS and then proposes a generalization to determine all LCS of the given pair of sequences. Earlier hardware algorithms were concerned with determining only the length of LCS or the edit distance of two sequences.<>
{"title":"Determining longest common subsequences of two sequences on a linear array of processors","authors":"A. Mukherjee","doi":"10.1109/ASAP.1992.218547","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218547","url":null,"abstract":"This paper presents special-purpose linear array processor architecture for determining longest common subsequences (LCS) of two sequences. The algorithm uses systolic and pipelined architectures suitable for VLSI implementation. The algorithms are also suitable for implementation on parallel machines. The author first develops a 'greedy' algorithm to determine some of the LCS and then proposes a generalization to determine all LCS of the given pair of sequences. Earlier hardware algorithms were concerned with determining only the length of LCS or the edit distance of two sequences.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129295437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218578
J. Levison, I. Kuroda, T. Nishitani
A building block for a scalable signal processor array is developed with a general-purpose DSP and a message routing LSI. Each DSP can be connected by multiple routing LSIs forming a point-to-point message-passing network with data packet communication. Low network latency is obtained by cut-through routing technique with sufficient communication bandwidth. The employment of an on-chip routing table allows regular as well as irregular topologies with complex routing techniques such as broad/multi-casting and dynamic routing. The combination of DSPs ( mu PD77240), a flexible message-passing network and an optional application-specific I/O interface makes the processor array suitable for a wide range of high speed signal processing applications such as adaptive array processing and 3-D vision processing.<>
{"title":"A reconfigurable processor array with routing LSIs and general purpose DSPs","authors":"J. Levison, I. Kuroda, T. Nishitani","doi":"10.1109/ASAP.1992.218578","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218578","url":null,"abstract":"A building block for a scalable signal processor array is developed with a general-purpose DSP and a message routing LSI. Each DSP can be connected by multiple routing LSIs forming a point-to-point message-passing network with data packet communication. Low network latency is obtained by cut-through routing technique with sufficient communication bandwidth. The employment of an on-chip routing table allows regular as well as irregular topologies with complex routing techniques such as broad/multi-casting and dynamic routing. The combination of DSPs ( mu PD77240), a flexible message-passing network and an optional application-specific I/O interface makes the processor array suitable for a wide range of high speed signal processing applications such as adaptive array processing and 3-D vision processing.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125505193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218582
Y. Hwang, Y. Hu
The authors present a more general mapping problem called multi-stage systolic mapping which focuses on the computing algorithms containing more than one nested loop constructs to be executed sequentially. Since the emerged interface problem now becomes the dominant factor in performing the mapping, the authors argue that the adjacent stages should have matched interface to reduce the overhead. For this, the conditions of interface matching between two stage's mappings are established. A systematic method to derive the interface matched mapping is also presented. To improve the performance degradation due to the initial and final phases of computation in systolic computing, the inter-stage computation concurrency is explored by overlapping part of the computations in successive stages and thus effectively reduces the computation latency. With these results, the multi-stage systolic mapping tool (MSSM) is developed and several design examples are presented to illustrate the potential use of MSSM.<>
{"title":"On systolic mapping of multi-stage algorithms","authors":"Y. Hwang, Y. Hu","doi":"10.1109/ASAP.1992.218582","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218582","url":null,"abstract":"The authors present a more general mapping problem called multi-stage systolic mapping which focuses on the computing algorithms containing more than one nested loop constructs to be executed sequentially. Since the emerged interface problem now becomes the dominant factor in performing the mapping, the authors argue that the adjacent stages should have matched interface to reduce the overhead. For this, the conditions of interface matching between two stage's mappings are established. A systematic method to derive the interface matched mapping is also presented. To improve the performance degradation due to the initial and final phases of computation in systolic computing, the inter-stage computation concurrency is explored by overlapping part of the computations in successive stages and thus effectively reduces the computation latency. With these results, the multi-stage systolic mapping tool (MSSM) is developed and several design examples are presented to illustrate the potential use of MSSM.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126581936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218572
R. Owens, M. J. Irwin, T. Kelliher, M. Vishwanath, R. Bajwa
This paper describes the design and implementation of high performance micrograined architectures. These architectures are capable of teraops performance. Each architecture is organized as a systolic array of processors. A prototyping system for the architectures is proposed. The prototyping system provides control, I/O, and an interface to a host system for each of the micro-grained architectures. The prototyping system has been designed with flexibility in mind to support a wide variety of these micro-grained architectures. Beyond the research outlined, the authors anticipate using the prototyping system as a 'test-bed' for various class/student VLSI design projects within the department. Three micro-grained architectures are described: an associative memory-based architecture, a Mux-based architecture and a RAM-based architecture. These architectures are useful for solving a number of important problems, such as: edge detection, locating connected components, two-dimensional signal and image processing, sorting elements, and performing element permutations.<>
{"title":"Implementing a family of high performance, micrograined architectures","authors":"R. Owens, M. J. Irwin, T. Kelliher, M. Vishwanath, R. Bajwa","doi":"10.1109/ASAP.1992.218572","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218572","url":null,"abstract":"This paper describes the design and implementation of high performance micrograined architectures. These architectures are capable of teraops performance. Each architecture is organized as a systolic array of processors. A prototyping system for the architectures is proposed. The prototyping system provides control, I/O, and an interface to a host system for each of the micro-grained architectures. The prototyping system has been designed with flexibility in mind to support a wide variety of these micro-grained architectures. Beyond the research outlined, the authors anticipate using the prototyping system as a 'test-bed' for various class/student VLSI design projects within the department. Three micro-grained architectures are described: an associative memory-based architecture, a Mux-based architecture and a RAM-based architecture. These architectures are useful for solving a number of important problems, such as: edge detection, locating connected components, two-dimensional signal and image processing, sorting elements, and performing element permutations.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125914969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218553
S. Olariu, J. L. Schwing, Jingyuan Zhang
Interval graphs provide a natural model for a vast number of scheduling and VLSI problems. A variety of interval graph problems have been solved on the PRAM family. Recently, a powerful architecture called the reconfigurable mesh has been proposed: in essence, a reconfigurable mesh consists of a mesh-connected architecture augmented by a dynamically reconfigurable bus system. It has been argued that the regular structure of the reconfigurable mesh is suitable for VLSI implementation. The authors develop a set of tools and show how they can be used to devise constant time algorithms to solve a number of interval-related problem on reconfigurable meshes. These problems include finding a maximum independent set, a minimum clique cover, a minimum dominating set, a minimum coloring, along with algorithms to compute the shortest path between a pair of intervals and, based on the shortest path, an algorithm to find the center of an interval graph. More precisely, with an arbitrary family of n intervals as input, all their algorithms run in constant time on a reconfigurable mesh of size n*n.<>
{"title":"Interval-related problems on reconfigurable meshes","authors":"S. Olariu, J. L. Schwing, Jingyuan Zhang","doi":"10.1109/ASAP.1992.218553","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218553","url":null,"abstract":"Interval graphs provide a natural model for a vast number of scheduling and VLSI problems. A variety of interval graph problems have been solved on the PRAM family. Recently, a powerful architecture called the reconfigurable mesh has been proposed: in essence, a reconfigurable mesh consists of a mesh-connected architecture augmented by a dynamically reconfigurable bus system. It has been argued that the regular structure of the reconfigurable mesh is suitable for VLSI implementation. The authors develop a set of tools and show how they can be used to devise constant time algorithms to solve a number of interval-related problem on reconfigurable meshes. These problems include finding a maximum independent set, a minimum clique cover, a minimum dominating set, a minimum coloring, along with algorithms to compute the shortest path between a pair of intervals and, based on the shortest path, an algorithm to find the center of an interval graph. More precisely, with an arbitrary family of n intervals as input, all their algorithms run in constant time on a reconfigurable mesh of size n*n.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117118916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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