Tzung-Je Lee, Chia-Ming Chang, Tzu-Chiao Sung, Chua-Chin Wang
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引用次数: 2
Abstract
A 10-bit 400-MS/s current-steering DAC is proposed in this paper. A proposed process detector, and a current calibration circuit are used in the binary current cells to calibrate the current error due to the process variation. Besides, an auxiliary delay circuit is employed in the current cell to turn off the additional calibration current. The proposed DAC is implemented using a typical 0.18 μm 1P6M CMOS process. With the proposed process calibration circuit and delay compensation, the design complexity and core area is dramatically reduced. The core area is 0.29 × 0.20 mm2. Besides, the worst DNL and INL of the DAC are simulated to be 0.18 LSB and 0.32 LSB, respectively. The power consumption is 3.7 mW.
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