Kameswaran Vengattaramane, J. Borremans, M. Steyaert, J. Craninckx
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引用次数: 8
Abstract
This paper presents a standard-cell based All-Digital Time-to-Digital Converter with reconfigurable resolution reaching sub-gate delay. The architecture based on spatial oversampling is implemented with an automated digital design flow. It features a robust online background calibration scheme for gain tracking. A 90 nm prototype chip achieves [39–14] ps effective resolution consuming [1–8] mA, in an area of only 0.26 mm2
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