Design of Ultra-Low Power Combinational Standard Library Cells Using A Novel Leakage Reduction Methodology

Abstract

Leakage power loss is a major concern as it drains the battery even when a circuit is completely idle. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, the design and characterization of an ultra-low power combinational CMOS standard cell library is presented. A novel technique that achieves cancellation of leakage effects in both the pull-up network (PUN) as well as the pull-down network (PDN) of CMOS cells is presented. A combination of high-VT and standard-VT sleep transistors is used for voltage balancing in the PUN and PDN paths. Experimental results show significant leakage power savings (average of 21X for a 180 nm process technology at 27degC) in CMOS library cells employing this sleep-circuitry when compared to standard CMOS cells.