Design and Implementation of OCP-PUF Based on FPGA

Abstract

With the rapid development of information technology, the number of Internet of things devices is growing rapidly, and the need to ensure its information security is becoming more and more urgent. In this application context, as a lightweight hardware encryption primitive, physical unclonable functions come onto the stage. This paper proposes a software PUF design, OCP-PUF, based on the internal timing difference of the processor. This PUF is based on the difference of the delay path in the processor pipeline, takes a specific instruction group input as a challenge, and response based on the instruction error that occurs after the clock overclocking. This design does not need to configure any additional hardware resources, nor does it need to make any changes to the hardware of the device. So it can be easily deployed on existing devices, which fits the current application background of low power consumption and low resource occupation. In the work of this paper, its principle and incentive response mechanism are described in detail, and its implementation based on RISC-V instruction set architecture on FPGA platform is verified and analyzed. The results verify that its uniqueness and stability are similar to that of traditional PUF, but it reduces resource occupation.