Physical compact modeling of layout dependent metal resistance in integrated LDMOS power devices

M.L. Kniffin, R. Thoma, J. Victory
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引用次数: 5

Abstract

Including the effects of parasitic metal resistance and their dependence on device layout is crucial to accurate modeling of large area LDMOS devices. This paper presents the derivation and use of compact analytical model equations for accurately predicting the Rdson performance of large area LDMOS devices. Results are compared with both numerical simulations and experimental measurements.
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集成LDMOS功率器件中布局相关金属电阻的物理紧凑建模
考虑寄生金属电阻的影响及其对器件布局的依赖关系对大面积LDMOS器件的精确建模至关重要。本文提出了紧凑解析模型方程的推导和应用,以准确地预测大面积LDMOS器件的Rdson性能。对数值模拟和实验测量结果进行了比较。
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Complementary LDMOS transistors for a CMOS/BiCMOS process Using "Adaptive resurf" to improve the SOA of LDMOS transistors Evaluation of 600 V/100 A NPT-IGBT with a non-self-align shallow p-well formation techniques A novel free wheeling diode for 1700 V IGBT module Low voltage CMOS compatible power MOSFET for on-chip DC/DC converters
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