Heegon Kim, Jingook Kim, B. Achkir, C. Yoon, J. Fan
{"title":"On-chip voltage regulator module (VRM) effect on power/ground noise and jitter at high-speed output buffer","authors":"Heegon Kim, Jingook Kim, B. Achkir, C. Yoon, J. Fan","doi":"10.1109/ISEMC.2014.6898946","DOIUrl":null,"url":null,"abstract":"On-chip voltage regulator module (VRM) for the reduction of power/ground noise on power distribution network (PDN) and jitter minimization at high-speed output buffer is introduced. The basic topology and optimized operation for on-chip VRM is analyzed. A PDN with on-chip VRM shows reduced power/ground noise through removing additional effects coming from package/PCB PDN. Also, when on-chip VRM is implemented on PDN of high-speed output buffers, jitter at output signal is lower. Improvements on PDN and jitter through on-chip VRM are shown and validated with SPICE simulation with 110nm CMOS technology library.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISEMC.2014.6898946","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
On-chip voltage regulator module (VRM) for the reduction of power/ground noise on power distribution network (PDN) and jitter minimization at high-speed output buffer is introduced. The basic topology and optimized operation for on-chip VRM is analyzed. A PDN with on-chip VRM shows reduced power/ground noise through removing additional effects coming from package/PCB PDN. Also, when on-chip VRM is implemented on PDN of high-speed output buffers, jitter at output signal is lower. Improvements on PDN and jitter through on-chip VRM are shown and validated with SPICE simulation with 110nm CMOS technology library.