Near time optimal recovery in a digitally current mode controlled buck converter driving a CPL

2018 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2018-03-04 DOI:10.1109/APEC.2018.8341027

Rabisankar Roy, S. Kapat

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引用次数: 2

Abstract

Stability of a distributed power architecture (DPA) still remains a major concern, even though individual stand-alone DC-DC converters are designed with sufficient (small-signal) stability margins. In such architectures, a tightly regulated point-of-load (PoL) converter resembles a constant power load (CPL) which introduces a negative-impedance effect to the source converter. This effect may introduce limit cycle oscillation (LCO) and may eventually destabilize the overall DPA. In this paper, a source buck converter is considered under digital current-mode control (DCMC) with a proportional-integral (PI) voltage controller, which is driving a CPL buck converter. During a power step-transient in the CPL, stable controller gain ranges under DCMC are computed for the source converter for individual operating conditions. Thereafter, a phase-plane based geometric framework is proposed to compute the optimal proportional gain for the source converter to achieve near time optimal recovery. A hardware prototype is made with 50 W nominal power ratings for individual converters. Analytical predictions and improved performance are validated experimentally.

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驱动CPL的数字电流模式控制降压变换器的近时间最优恢复

分布式电源架构(DPA)的稳定性仍然是一个主要问题，即使单个独立的DC-DC转换器设计有足够的(小信号)稳定裕度。在这样的架构中，严格调节的负载点(PoL)转换器类似于恒定功率负载(CPL)，它为源转换器引入了负阻抗效应。这种效应可能会引入极限环振荡(LCO)，并最终使整个DPA不稳定。本文考虑在数字电流模式控制(DCMC)下，采用比例积分(PI)电压控制器驱动CPL降压变换器。在CPL的功率阶跃暂态过程中，计算了源变换器在DCMC下的稳定控制器增益范围。然后，提出了一种基于相平面的几何框架来计算源变换器的最优比例增益，以实现近时间最优恢复。硬件原型是由50 W额定功率的个别转换器。通过实验验证了分析预测和改进的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2018 IEEE Applied Power Electronics Conference and Exposition (APEC)

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