Immunity modelling of electronics board

Abstract

Electronic boards will become higher density of integration with lower supply voltages. Internal integrated Circuits have more and more gates on silicon and Printed circuits Boards use many high density technologies. That size reduction integration with nearby signals positions promotes internal crosstalk, sizes reduction of die geometries increases unwanted current in parasitic structure as isolation capacitances. Consequently, the immunity of electronic boards is becoming more and more critical and the use of models and simulation tools is hardly required to optimize during the design phases the susceptibility behaviour and also to predict the immunity strength to conducted disturbances both at the IC and the application level. This paper introduces in section I an overview of the IEC projects for Integrated Circuit modelling. An immunity model for an electronic board is described in section II. Example model of driver bus is presented in a part III. Simulation results of a immunity test with that driver immunity model is presented in a part IV.