Heterogeneous design methodology with configurable regular topology set for scalable Network-on-Chip designs

Abstract

The NoC (network-on-chip) paradigm is commonly considered as an aggressive long-term approach for on-chip communication. Interconnection networks of regular topologies can be designed as IP cores to reduce the well known design-productivity gap. Therefore, regular topologies are more preferred than irregular topologies. To solve the scalability problem of the NoC designs with homogeneous regular topologies, we propose a new NoC design methodology that uses heterogeneous regular topologies. We illustrate the proposed heterogeneous design methodology with a simple configurable regular interconnect topology set, which consists of three subtopologies with different network performances and silicon overheads. Evaluation of the three subtopologies reveals that subtopologies with more connections result in better network performance and more wire complexity. The contribution of the proposed heterogeneous design methodology is that it provides a flexible way to scale the interconnection networks of regular topologies according to the traffic requirements.